category: Power Awareness

category: IoT, Security & Automotive

Aging Analysis Hits Mainstream
By Ann Mutschler - 08 Nov, 2018 - Comments: 1

Given the ever increasing challenge of designing high-reliability ICs – especially for automotive, medical, industrial, and aerospace and defense applications – the inclusion of aging analysis capabilities is on the rise in EDA tools as well as design IP. The issue comes down to predictability of devices as they operate. As discussed in, “Taming NBTI To Improve Device Reliability,” t... » read more

ML Becomes Useful For Variation Coverage
By Ann Mutschler - 11 Oct, 2018 - Comments: 0

According to industry sources, it is quite a feat to get a chip back from the foundry that actually meets the specifications the design team worked towards, and because of this much effort is underway across the industry to understand what will happen to a design once it reaches the manufacturing stage, and what the effects of design choices actually are. AI and ML are absolutely the buzz wo... » read more

Heterogeneous Hubbub
By Ann Mutschler - 08 Mar, 2018 - Comments: 0

It’s no secret that designers today would prefer not to be restricted in their architectural choices. And who can blame them? At the same time, this sentiment has boosted interest and usage of both heterogenous architectures as well as the RISC-V ISA. To support this, companies across the design, test and verification ecosystem are ramping efforts. One such effort is the teaming of UltraSo... » read more

Getting Power Management Right
By Ann Mutschler - 14 Nov, 2017 - Comments: 0

Getting power management right in the era of heterogeneous SoCs is a multi-pronged effort, there's no getting around it. Engineering teams daily try to squeeze more and more power from their designs, which many times includes adding human resources and expertise to the project. Take an example where a design team leader gets the mandate to include high level synthesis in the design metho... » read more

The Evolving Data Center
By Ann Mutschler - 12 Oct, 2017 - Comments: 0

Confession time. In addition to being utterly fascinated by all things chip design, I have always been absolutely enthralled by the magnificent data center. With a family member that has worked in them for most of his career, I can recalled being delighted to be amongst the racks in a second floor data center in Palo Alto in the early 90s. Time to time throughout my career it’s been thrilling... » read more

DARPA CHIPS Program Pushes For Chiplets
By Ann Mutschler - 14 Sep, 2017 - Comments: 0

While the semiconductor industry plugs away at More Than Moore innovation, the U.S. government is guiding its own SoC development. A new program kicked off last year called ‘Common Heterogeneous Integration and IP Reuse Strategies’ or CHIPS to take its own approach the incredibly high cost of SoC design and manufacturing. DARPA said it recognizes that the explosive growth in mobile and t... » read more

Computer Vision Powers Startups, Bleeding Edge Processes
By Ann Mutschler - 10 Aug, 2017 - Comments: 0

You can’t turn around these days without walking into a convolutional neural network…..oh wait, maybe not yet, but sometime in the not-too-distant future, we’ll be riding in vehicles controlled by them. While not a new concept, CNNs are finally making the big time, as evidenced by a significant upswell in startup activity, tracked by Chris Rowen, CEO of Cognite Ventures. According to h... » read more

Who’s Responsible For Transistor Aging Models?
By Ann Mutschler - 13 Jul, 2017 - Comments: 0

While there are a number of ways to go about reliability and transistor aging analysis, it is all in large part dependent on fabs and foundries to provide the aging models. The situation is also not entirely clear in the semiconductor ecosystem because the classic over-the-wall mentality between design and manufacturing still exists. And unfortunately this wall is bi-directional. Not only... » read more

ESD Guns, Transients And Testing…Oh My!
By Ann Mutschler - 08 Jun, 2017 - Comments: 0

With the pervasiveness of power management techniques like clock gating and power gating, transient power is on the rise, accompanied by the requirement to closely examine a system for such phenomenon as electrostatic discharge. I was interested to recently learn more about ESD testing, some of which is done with software tools, but much is still done in the lab with prototypes of the end d... » read more

Power Just One Piece Of The Puzzle At 10nm And Below
By Ann Mutschler - 11 May, 2017 - Comments: 0

With dynamic power density and rising leakage power becoming more problematic at each new node, it is more important than ever to look at designs today with power in mind from the very start. As part of this complex picture of electronic design today, every piece in the design flow must tie together for the greatest efficiency and optimization. While this is partly power, there are more... » read more

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