Technical Conferences: The Insurmountable Opportunity

By Mike Gianfagna - 26 Jul, 2018 - Comments: 0

As a technology marketeer, I’m always looking for high-leverage events to promote our brand and gain visibility for new products and services. Let’s face it, this is the main benefit for attending a technical conference or a trade show. While the dream might be 40+ leads that are well-qualified and closable in the quarter, the reality is more of a long-game kind of strategy. For years, t... » read more

FinFET ASICs: It Takes A Platform

By Mike Gianfagna - 28 Jun, 2018 - Comments: 0

Sophisticated, specialized ASIC technology is making an impact on the everyday world around us. Whether it’s a gadget you can have a conversation with, a car that will take over driving from time to time, or internet speeds that seem impossibly fast, there is likely sophisticated custom silicon present as a critical enabling technology. Plenty has been written about advanced ASICs for network... » read more

Deep Learning And The Future

By Mike Gianfagna - 26 Apr, 2018 - Comments: 1

Following up from my last post on our deep learning event at the Computer History Museum – “ASICs Unlock Deep Learning Innovation,” I’d like to take a glimpse into the future. Like many such discussions, it’s often useful to take a look back first to try and make sense out of what is to come. That’s essentlially what our keynote speaker, Ty Garibay, did at the event. Ty is the CTO... » read more

Deep Learning Market Forces

By Mike Gianfagna - 22 Mar, 2018 - Comments: 0

Last week, eSilicon participated in a deep learning event at the Computer History Museum – “ASICs Unlock Deep Learning Innovation.” Along with Samsung, Amkor Technology and Northwest Logic, we explored how our respective companies form an ecosystem to develop deep learning chips for the next generation of applications. We also had a keynote presentation on deep learning from Ty Garibay, C... » read more

Deconstructing Deep Learning

By Mike Gianfagna - 22 Feb, 2018 - Comments: 0

I discuss AI and deep learning a lot these days. The discussion usually comes back to “what is a deep learning chip?” These devices are basically hardware implementations of neural networks. While neural nets have been around for a while, what’s new is the performance advanced semiconductor technology brings to the party. Applications that function in real time are now possible. But wh... » read more

In Case You Missed It

By Mike Gianfagna - 25 Jan, 2018 - Comments: 0

We recently held two very successful seminars in Tokyo and Shanghai. Samsung Memory presented their HBM2 solutions, Samsung Foundry talked about their advanced 14nm FinFET solutions, ASE Group reviewed their advanced 2.5D packaging solutions, eSilicon presented our ASIC and 2.5D design/implementation and IP solutions, Rambus detailed their high-performance SerDes solutions and Northwest Logic p... » read more

What’s Next?

By Mike Gianfagna - 21 Dec, 2017 - Comments: 0

We just concluded two very successful seminars in Tokyo and Shanghai. Samsung Memory presented their HBM2 solutions, Samsung Foundry talked about their advanced 14nm FinFET solutions, ASE Group reviewed their advanced 2.5D packaging solutions, eSilicon presented our ASIC and 2.5D design/implementation and IP solutions, Rambus detailed their high-performance SerDes solutions and Northwest Logic ... » read more

Advanced ASICs: It Takes An Ecosystem

By Mike Gianfagna - 30 Nov, 2017 - Comments: 0

I remember the days of the IDM (integrated device manufacturer). For me, it was RCA, where I worked for 15 years as the company changed from RCA to GE and then ultimately to Harris Semiconductor. It’s a bit of a cliché, but life was simpler then, from a customer point of view at least. RCA did it all. We designed all the IP, did the physical design, owned fabs, assembly and test facilities a... » read more

Talking The Talk On Training

By Mike Gianfagna - 28 Sep, 2017 - Comments: 1

In my prior post, I discussed the value of good design flow training. A properly executed program can turn average engineers into above average problem solvers with the right tools and techniques. We got to thinking about this opportunity quite seriously at eSilicon. Is there a way to develop a focused, intense training program to create a new “army” of elite designers? In short, we thin... » read more

Training As A Strategic Weapon

By Mike Gianfagna - 24 Aug, 2017 - Comments: 0

In my last post, I discussed the topic of applying machine learning to the design of machine learning chips. I pointed out that one can achieve significant improvements in schedule predictability, PPA compliance and an overall reduction in program risk if machine learning is applied to the right kind of knowledge base. This is very real, and we are seeing the benefits of this approach daily. Bu... » read more

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Knowledge Centers
Entities, people and technologies explored

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A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

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by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

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