category: Whitepapers

category: IoT, Security & Automotive

Plug-And-Play Test Strategy For 3D ICs
By Various Writers - 26 Feb, 2014 - Comments: 0

As the industry transitions to 3D ICs, new test strategies are being developed to meet to two 3D IC test goals: improving the pre-packaged test quality and establishing new tests between the stacked die. Solutions for 3D IC test are developing rapidly and are based on mature technologies. In this paper, we describe a test strategy for 3D ICs based on a plug-and-play architecture that allows die... » read more

Maximizing Verification Effectiveness Using Metric-Driven Verification
By Various Writers - 26 Feb, 2014 - Comments: 0

This paper introduces the Cadence Incisive Verification Kit as a golden example of how to maximize verification effectiveness by applying metric-driven verification (MDV) in conjunction with the Universal Verification Methodology (UVM). MDV provides an overarching approach to the verification problem by transforming an open-ended, open-loop verification process into a manageable, repeatable, de... » read more

Impact Of Illumination On Model-Based SRAF Placement For Contact Patterning
By Various Writers - 19 Feb, 2014 - Comments: 1

Sub-Resolution Assist Features (SRAFs) have been used extensively to improve the process latitude for isolated and semi-isolated features in conjunction with off-axis illumination. These SRAFs have typically been inserted based upon rules which assign a global SRAF size and proximity to target shapes. Additional rules govern the relationship of assist features to one another, and for random log... » read more

How A Team-Based Approach To PCB Power Integrity Analysis Yields Better Results
By Various Writers - 12 Feb, 2014 - Comments: 0

Assuring power integrity of a PCB requires the contributions of multiple design team members. Traditionally, such an effort has involved a time-consuming process for a back-end-focused expert at the front end of a design. This paper examines a collaborative team-based approach that makes more efficient use of resources and provides more impact at critical points in the design process. To vie... » read more

Full-Chip IC ESD Integrity
By Various Writers - 12 Feb, 2014 - Comments: 0

ESD or electro-static discharge induced field failures for integrated circuits (IC) has always been an challenge. Literature survey indicates that as high as 35% of total chip field failures are ESD related. Several trends in the IC industry are exacerbating the impact of ESD induced failures: (a) move towards advanced processing technologies with shrinking geometries, (b) push for higher... » read more

Debugging Graphics Synchronization Issues With Sourcery Analyzer
By Various Writers - 12 Feb, 2014 - Comments: 0

The modern user interface (UI) has come of age. UIs are ubiquitous among many of the more popular consumer electronic products in use today, from mobile phones and smart appliances to automotive in-vehicle (IVI) systems. In many ways, the UI is the only interaction a consumer has with an embedded system so it has to work perfectly with very little room for error. To download this white paper... » read more

Clock Gating Optimization At RTL
By Various Writers - 12 Feb, 2014 - Comments: 0

In today’s semiconductor designs, lower power consumption is mandatory for mobile and hand-held applications for longer battery life and for networking or storage devices for low carbon footprint requirements. Clock power can consume as much as 60% to 70% of total chip power and is expected to increase further in the more advanced technology nodes. Hence, reducing clock power is very importan... » read more

Designing An Efficient Multi-Core LTE-A Modem
By Various Writers - 12 Feb, 2014 - Comments: 0

LTE-Advanced represents the next generation mobile broadband, and in turn throws the challenge to the designers to create highly power efficient mobile devices capable of delivering these services. ARM, the leading supplier of embedded processors, physical IP and inter-connect fabric, along with CEVA propose a joint analysis looking at the design considerations that are required to realize the ... » read more

Reduce Power, Area And Routing Congestion
By Various Writers - 12 Feb, 2014 - Comments: 0

This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare Interconnect Fabric for the ARM® AMBA 3 AXI while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to... » read more

Localized, System-Level Protocol Checks and Coverage Closure Using Veloce
By Various Writers - 29 Jan, 2014 - Comments: 0

Broadcom recently developed a unified, scalable, verification methodology based on the Veloce emulation platform. In order to test this new environment, they ran a test case, which proved that they can take assertions, compile them into Veloce, and verify that they fire accurately. In so doing, they were able to provide proof of concept for their primary goal: the creation of an internal flow t... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy