Ins And Outs Of In-Circuit Monitoring


At 7nm and 5nm, in-circuit monitoring is becoming essential. Steve Crosher, CEO of Moortec, talks about the impact of rising complexity, how different use cases and implementations can affect reliability and uptime, and why measuring electrical, voltage and thermal stress can be used to statistically predict failures and improve reliability throughout a chip’s lifetime. » read more

3 Types Of AI Hardware


As AI chips become more pervasive, three primary approaches are moving to the forefront. Bradley Geden, director of product marketing at Synopsys, looks at how to take advantage of repeatability, what the different flavors look like, the difference between flat and hierarchical design, and what impact black-box arrays have on programmability. » read more

Increasing eFPGA Density


How to boost embedded FPGA density to the point where it is competitive with traditional FPGAs, at a lower cost and faster turnaround time. Geoff Tate, CEO of Flex Logix, talks about the importance of interconnects and standard cells in adding flexibility into chips, and why eFPGAs are suddenly gaining attention. » read more

Using ML In Manufacturing


How to prevent early life failures by applying machine learning to different use cases, and how to interpret models for different tradeoffs on reliability. Jeff David, vice president of AI solutions at PDF Solutions, digs down into how to utilize data to improve reliability. » read more

Different Levels Of Interconnects


The interconnect hierarchy from metal 0 in a semiconductor all the way up to racks of servers. Kurt Shuler, vice president of marketing at Arteris IP, explains why each one is different, and how every level can contribute to latency and performance. » read more

DAC 2020: Virtual And Different


Zhuo Li, group director at Cadence, and Harry Foster, chief scientist at Mentor, a Siemens Business, talk about the changes in content for this year's Design Automation Conference. » read more

High-Speed SerDes At 7/5nm


Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how to optimize PHYs for integration on all four corners of an SoC, as well as the PPA implications of moving large amounts of data across and around a chip. » read more

Ensuring HBM Reliability


Igor Elkanovich, CTO of GUC, and Evelyn Landman, CTO of proteanTecs, talk with Semiconductor Engineering about difficulties that crop up in advanced packaging, what’s redundant and what is not when using high-bandwidth memory, and how continuous in-circuit monitoring can identify potential problems before they happen. » read more

Cleaning Data For Final Test


John O’Donnell, CEO of yieldHUB, talks about why data integrity is so critical for final test, what can cause it to be less-than-perfect, what’s needed to improve the quality of that data, and how that impacts the overall yield in a fab. » read more

Rising Packaging Complexity


Synopsys’ Rita Horner looks at the design side of advanced packaging, including how tools are chosen today, what considerations are needed for integrating IP while maintaining low latency and low power, why this is more complex in some ways than even the most advanced planar chip designs, and what’s still missing from the tool flow. » read more

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