Big Changes For eFPGAs

By Ed Sperling - 11 May, 2020 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks with Semiconductor Engineering about the state of embedded FPGAs, why this is easier for some companies than others, why this is important for adding flexibility into an ASIC, and what are the main applications for this technology. » read more

Who Owns A Car’s Chip Architecture

By Ed Sperling - 05 May, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris IP, examines the competitive battle brewing between OEMs and Tier 1s over who owns the architecture of the electronic systems and the underlying chip hardware. This has become a growing point of contention as both struggle for differentiation in a market where increasingly autonomous vehicles will all behave the same way. That, in turn, has si... » read more

Using Big Data For Yield And Reliability

By Ed Sperling - 22 Apr, 2020 - Comments: 0

John O’Donnell, CEO of yieldHUB, talks about the importance of clean data for traceability, yield improvement and device reliability, where and how it gets cleaned, and why that needs to be accompanied by domain expertise. » read more

DDR PHY Training

By Ed Sperling - 21 Apr, 2020 - Comments: 0

Brett Murdock, senior product marketing manager at Synopsys, explains how to train the DRAM physical layer using firmware, why that is so important for flexibility, and what kinds of issues engineers encounter when using this approach. » read more

Stream Vs. Pool Data Processing

By Ed Sperling - 08 Apr, 2020 - Comments: 0

Geoff Tate, CEO of Flex Logix, looks at the very different data processing requirements at the edge and in the data center, and what really drives efficiency and speed in applications such as automotive. » read more

Last-Level Cache

By Ed Sperling - 06 Apr, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources. » read more

PCIe 5.0 Drill-Down

By Ed Sperling - 01 Apr, 2020 - Comments: 0

Suresh Andani, senior director of product marketing for SerDes IP at Rambus, digs into the new PCI Express standard, why it’s so important for data centers, how it compares with previous versions of the standard, and how it will fit into existing and non-von Neumann architectures. » read more

Building A Safety Verification Flow

By Ed Sperling - 24 Mar, 2020 - Comments: 0

Sal Alvarez, senior manager of application engineering at Synopsys, explains how safety verification differs from functional verification, what changes with failure mode effects analysis, and how to determine and verify the effectiveness of safety features. » read more

Speeding Up Verification Using SystemC

By Ed Sperling - 23 Mar, 2020 - Comments: 0

Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

Timing Closure At 7/5nm

By Ed Sperling - 17 Mar, 2020 - Comments: 2

Mansour Amirfathi, director of application engineering at Synopsys, examines how to determine if assumptions about design are correct, how many cycles are needed for a particular operation and why this is so complicated, and what happens if signals get out of phase. » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

category: Videos

category: IoT, Security & Automotive

Big Changes For eFPGAs

Who Owns A Car’s Chip Architecture

Using Big Data For Yield And Reliability

DDR PHY Training

Stream Vs. Pool Data Processing

Last-Level Cache

PCIe 5.0 Drill-Down

Building A Safety Verification Flow

Speeding Up Verification Using SystemC

Timing Closure At 7/5nm

Trending Articles

Hybrid Bonding Makes Strides Toward Manufacturability

Americas Chip Funding Energizes Industry

Advanced Packaging Driving New Collaboration Across Supply Chain

Chiplets Make Progress Using Interconnects As Glue

2D Semiconductors Make Progress, But So Does Silicon

Knowledge Centers
Entities, people and technologies explored