Roundtable: What’s Changing In System-Level Design

By Ed Sperling - 26 Jan, 2012 - Comments: 0

System-Level Design talks about what's changing and what's needed with Juan Rey of Mentor Graphics: Yervant Zorian of Synopsys; Michael McNamara of Cadence; Prasad Subramaniam of eSilicon; and Ravi Varadarajan of Atrenta. [youtube vid=8siiKBKD0-k] » read more

Making Software Better

By Ed Sperling - 11 Jan, 2012 - Comments: 0

Low-Power Engineering talks about what will make software more energy-efficient with Pete Hardee, marketing director at Cadence; Adam Kaiser, Nucleus RTOS architect at Mentor Graphics; Chris Rowen, CTO of Tensilica; Vic Kulkarni, senior VP and General Manager of Apache Design, and Bill Neifert, CTO of Carbon Design. [youtube vid=Jxquj8K8_BA] » read more

Tech Talk: Comparing Smart Phones

By Ed Sperling - 15 Dec, 2011 - Comments: 0

What makes one smart phone last longer on a charge than another? The answer may surprise you. Low-Power Engineering talks with Cary Chin, director of technical marketing for low-power solutions at Synopsys, about what his months of research have shown. [youtube vid=BUefmd_oFp8] » read more

Executive Briefing: The End Of CMOS?

By Ed Sperling - 14 Dec, 2011 - Comments: 0

Steve Longoria, senior vice president of Soitec, talks with System-Level Design about why silicon on insulator has suddenly become essential to semiconductor manufacturing and what it will mean for Moore's Law. [youtube vid=kNl1RSEpqKc] » read more

Time For FD-SOI?

By Ed Sperling - 12 Dec, 2011 - Comments: 0

Paul Boudre, COO of Soitec, talks with Semiconductor Manufacturing & Design about why SOI has suddenly become so interesting in semiconductor manufacturing and how it will affect the move to FinFETs. [youtube vid=DO9zfrinbOg] » read more

Using High-Level Synthesis To Manage Power

By Ed Sperling - 02 Nov, 2011 - Comments: 0

Low-Power Engineering talks with Apache Design's Vic Kulkarni, Tensilica's Grant Martin, Cadence's Mike Meyer, Calypto's Shawn McCloud and Forte Design's Brett Cline about the need for a higher level of abstraction to optimize power in ICs. [youtube vid=gpWacAhMYgo] » read more

Executive Briefing: 3D IC Stacking Challenges

By Ed Sperling - 21 Sep, 2011 - Comments: 0

Sonics CEO Grant Pierce sounds off on the challenges of stacking die, what has to change and why. [youtube vid=wCseVs738LQ] » read more

Tech Talk: Graphic Headaches

By Ed Sperling - 24 Aug, 2011 - Comments: 0

Nvidia senior vice president of GPU engineering Jonah Alben talks with System-Level Design about the challenges of designing a graphics chip at advanced process nodes. [youtube vid=3Nc77aVH94g] » read more

The Challenge of 3D

By Ed Sperling - 06 Jul, 2011 - Comments: 0

Juan Rey, senior director of engineering for Mentor Graphics' Design To Silicon Division, talks about 3D stacking and 3D structures on chips. [youtube vid=YiH5IkxiEHU] » read more

State Of The Semiconductor industry

By Ed Sperling - 06 Jul, 2011 - Comments: 0

Jonathan Davis, executive vice president of SEMI, drills down into the state of the chip industry, what's driving the changes and what the big issues are for manufacturing and design in the future. [youtube vid=pjp5i3N1Cw4] » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

category: Videos

category: IoT, Security & Automotive

Roundtable: What’s Changing In System-Level Design

Making Software Better

Tech Talk: Comparing Smart Phones

Executive Briefing: The End Of CMOS?

Time For FD-SOI?

Using High-Level Synthesis To Manage Power

Executive Briefing: 3D IC Stacking Challenges

Tech Talk: Graphic Headaches

The Challenge of 3D

State Of The Semiconductor industry

Trending Articles

Hybrid Bonding Makes Strides Toward Manufacturability

Americas Chip Funding Energizes Industry

Advanced Packaging Driving New Collaboration Across Supply Chain

Chiplets Make Progress Using Interconnects As Glue

2D Semiconductors Make Progress, But So Does Silicon

Knowledge Centers
Entities, people and technologies explored