Challenges In IC And Electronic Systems Verification

By Aveek Sarkar
Designing successful electronic systems that can meet the needs of a challenging and quickly evolving mobile market requires design teams to solve critical problems such as power efficiency, unrealistic schedules, and cost-down considerations. In this first of a three-part series, we will look at these challenges.

Part 1: The Growing Challenges
Designing electronic systems was never easy, especially given the underlying complexity involved. However, the need to pack the functionality of multiple hardware systems (GPS, gaming, computer, phone, etc.) into one system-on-chip (SoC) and still meet the thermal and battery life requirements of a hand-held mobile device has made power efficiency the top design criteria today. Design teams must achieve the maximum operating speed and end-user experience at the lowest power usage level. Differentiation in the smartphone processor and communication chipsets by delivering best-in-class MHz/mW performance and connectivity is becoming key as consumers increasingly standardize on the end operating system (IDC noted that three out of four smartphones shipped in the second half of 2012 were Android-based).

Likewise, design schedules were always important, but never as much as they are today when failing to ship a product in time for the holiday shopping season can mean significant market share losses. Still, having just one component of this complex system ready in time does not mean that the entire system will operate right the first time. An integrated circuit (IC) or SoC that meets 2GHz in timing simulations during the design process may not achieve the same clock frequency when used inside a system with its package and PCB. Waiting for physical prototypes to become available takes too long for today’s accelerated design cycles. Having a simulation-driven product development process in which each component, each sub-system, and the eventual system is simulated, optimized and signed-off in a virtual prototyping environment is not only critical, but also a requirement for achieving first-time success.

Design teams that consider cost as a design initiative are more likely to be rewarded with higher margins. Most electronic system design teams today are broken down by physical or organizational boundaries and often are not aware of how the component they are working on will be used in the next-level subsystem. So to compensate and to ensure their own protection, teams will over-design their part to guarantee that the final system will function properly. This practice can result in larger macro/IP sizes, or the use of an extra metal layer in the SoC, or the addition of more capacitors in the package, or an increased number of traces in the board (PCB)—each of which adds to the overall cost of the end-system. Therefore, having a design environment that allows various teams to share appropriate data for each component to help facilitate concurrent system-wide optimization is a must.

Let’s consider what constitutes an electronic system (see the figure below for components in a tablet device). Design teams typically look at the chip, the package, or the board individually. However, there is a growing trend to look at them as a whole. An electronic system such as a tablet has even more sub-components that must be verified individually, and then simulated together in order to understand the overall power consumption of the device, its operating clock frequency, its ability to communicate across multiple bands and modes, high-definition display capabilities, and its ability to have video functionality among other things.

Extreme integration creates complex new challenges for RF performance, system signal integrity, system-level electro-magnetic interference (EMI), low-power operations, and communications reliability. To produce a successful end product requires consideration for all these issues, as well as other aspects including touch-screen interface behavior, the mechanical and thermal stability of the entire system, FCC guideline compliance, and more. The successful tape out of a chip does not guarantee the success of the eventual end product, either. There are many variables and factors that must be taken into account first.

Various components that go into making today’s tablets.

The Desired Approach
In order to deliver competitive electronic systems for the rapidly evolving mobile market, design teams have to meet three key targets simultaneously: power efficiency, design schedules, and cost-down. A simulation-driven product development process enables both a top-down and a bottom-up analysis framework to meet the competing requirements of performance, power and price while adhering to project schedules.

The top-down planning process helps define higher-level goals or ‘budgets’ for the design of the system, its subsystems and components. For example, the thermal and battery life constraint for a next-generation smartphone dictates its end MHz/mW threshold. This helps the application processor team have a well-defined power budget to work towards. One way to ensure this target is met is by starting as early as possible. Power analysis at the register transfer language (RTL) design phase is becoming the norm given the speed, flexibility and the accuracy it provides. By analyzing power consumption for various operating modes, identifying and eliminating areas of wasted power (‘power bugs’) especially during idle modes of the chip, and by tracking the power through the design process, design teams can ensure that high-level power targets can be met and avoid costly late surprises.

The bottom-up process implies that each section of the design is individually verified in a virtual prototyping environment, with the appropriate level of detail, and the data created from each sub-component enabling the simulation of the next higher stage (or sub-system). An IC is first simulated in detail by itself with appropriate models of the system incorporated (system-aware IC sign-off), then accurate and representative models of the IC are created and used for system-level chip-aware power, timing, thermal and EMI simulations. For example, power integrity is a design signoff check to ensure proper at-speed operation of the IC at sub-1V supply levels. When verifying power integrity at the IC-level, the entire IC with 100+ unique power supply domains and associated chip-level details must be simulated, and include the impact of the system through appropriate package and board (PCB) parasitic models. At the next higher level while verifying the traces of the board (PCB), they must be simulated considering the current draw and parasitics for all the ICs residing on the board.

Another area where a step-by-step approach can be useful is to simulate and verify the operation of high-speed I/O interfaces, especially as data rates become faster and supply voltages get lower.

In the next two parts of this series, we will look at these challenges in more detail and outline specific steps and approaches.