Changes Ahead

With 3D stacked die looking increasingly promising, the question for much of the industry is exactly when this will happen, how it will happen, and what it will mean to the design process.

To a large extent, in an attempt to buffer the risk, much of the fabless industry has been heading toward FPGA prototypes. It is uncertain whether that trend will continue at the same pace as 3D processes mature and using standardized ASIC platforms becomes an option.

So far the answer isn’t clear, and it may not be the same for all fabless companies or at all stages of the 3D rollout. While IDMs will continue to develop most of the parts themselves, the big advantage of 3D is that fabless companies will be able to focus on what they do best and work around more standardized underpinnings. In planar chips that requires tweaking the base platform, which has made FPGA prototyping extremely popular. In 3D, that tweaking may be possible on a completely separate die and sometimes even in software, all of which will run atop a standard platform containing memory, a processor and the I/O.

This is a multi-year rollout, of course. The first chips from non-IDMs, which are expected to begin showing up in 2012, will likely be two layers. Those will be followed by three or more layers of silicon, all connected with through-silicon vias. During that time, ASIC platforms will become commoditized and standardized and FPGAs will have to follow the same route. In fact, it may be likely that FPGA prototyping will be replaced by FPGAs as part of the overall 3D structure if the programmable logic approach will succeed.

There is plenty of opportunity in this shift, and for EDA companies this may be the inflection point they have been waiting for. While they have had trouble competing with FPGA vendors, which subsidize their tools as part of the cost of the FPGA platform, the market for FPGA prototypes will likely remain flat or shrink as 3D stacking gains steam. And the complexity of 3D structures, complete with thermal and mechanical stress and power issues may dwarf the ability of layout tools that have become popular in FPGA floorplanning.

So far no one knows for sure what will happen in this market. But the writing is on the wall that change is coming, and in every change there are winners and losers. The only question is who’s going to be on which side.

–Ed Sperling