Chip Architect Challenges

Picking the best implementation path is only one part of the job. Planning for future derivatives and short market windows makes it much harder.


By Ann Steffora Mutschler
Product lifecycles can be shorter than the design cycle and even the process development cycle, particularly in the consumer handheld device market. It’s up to the chip architect to decide how the functions should be implemented.

The good news is there are a number of options available, ranging from mapping the design to 2.5D technology, moving to finFET transistors, to making sure the design is prototyped early enough to meet the market window.

“You can’t even design an SoC before the kids want a new gadget,” observed Subi Kengeri, vice president of advanced technology architecture in the office of the CTO at GlobalFoundries. “If you probe into this a little bit as to why the product lifecycle is shorter than the design cycle, it’s because the technology has gotten so complex. To design in that complex technology, number one, the EDA is becoming more and more complex so the runtimes of all the EDA tools is not easy. Number two, every time you have more transistors available to you in a new technology and you want to integrate them to get the best out of that technology, you are creating new functions and features so the SoCs are becoming complex. Number three, you need more designers to go and design more complexity—more manpower and brainpower. It’s not just bodies; it’s not just like any design engineer can design the advanced SoCs anymore because they are so complex you need skilled talent and that’s scarce.”

To make matters worse, with advanced technologies there are so many challenges that progress is slowing. And with investments ranging from $50 million to $80 million—and sometimes much higher—ROI becomes a major concern. “You can’t simply put in $50 million to $80 million, forget about it and move on to the next node without having recouped or leveraged that investment,” he said.

The product development cycle and the product longevity always have been an interesting mix. How they go together depends on the market segment and frequently the geography, as well.

“For the consumer electronics market, where one is hyper-obsessed with the SoC in cell phones, the longevity of the product is determined by the length of the contract, which are typically two years from the user’s perspective,” said Gene Matter, senior applications manager at Docea Power. “You upgrade your phone every two years. From the OEM developer’s perspective, the challenge is to release two to four huge model offerings at least two to three times a year. Then for the poor guy who is designing the base SoC in the platforms of the systems, typically you start with one major derivative and then minor derivatives from that.”

As such, the power architect must have a good mastery of the overall cadence and sequence of major product introductions, especially in the consumer electronics market. Key to this process are the availability of new IP and a new architecture.

“For the really, really good architects, you have the five-year roadmap,” Matter said. “You’ve already sequenced this out and you shouldn’t have a lot of surprises. If you do, it means you’re not doing your job well. If you don’t understand the sequence of your products, you don’t understand the dependencies of the operating system, the process technology…then you should find something else to do.”

Defining the future

If the power architect’s job is to take the technology that is available and to define the future, then they have to look well beyond the product into portfolio management. That job is similar to the platform architect, or in years past, the chief architect whose job was akin to a master builder.

“In the old days, the master builders of churches or master builders of the pyramids or master builders of anything had a long view/portfolio view of what they were doing, Matter said. “The power architect has to have this master builder approach. By that I mean you’ve got to look at the framework and structure of a power management architecture that can transcend just a single product implementation. You’ve got to think product family, product portfolio, technology portfolio. And it means the power architect has to really up-level his thinking to frameworks that are sensible and easily extensible, and which deliver the most value for the broadest set of products and can be optimized for the products.”

Optimization itself is a major challenge to be reckoned with. The optimization point for power 10 years ago was battery life. The optimization point for power now, particularly in the mobile market, is time between recharges and idle time. Especially in regard to idle power reduction because of increases in performance, Matter explained, “we can get a task done really, really quickly. Most of the time, it’s sitting around waiting for something to go do but the user doesn’t like to wait for a response, and they get really torqued off when their battery runs down–particularly when it’s doing absolutely nothing. So now the optimization point is about ‘instant on,’ always accessible, always available, always connected.”

With server and embedded applications, different power optimization points occur that are just as complicated, including managing power budget and power delivery, thermal virtualization, managing cooling capacity and cooling budgets. As a power architect, the big focus needs to be future power challenges and what framework should be applied. What should be extended and what should be updated to reflect the new optimization points?

Device choices reflect market pressure

With product lifecycles and design lifecycles very close to being aligned, design teams can’t afford to take 18 months to crank out an ASIC because if you do, you’re dead, suggested Kirk Saban, a senior product line manager at Xilinx. “Like Samsung says on their commercial, ‘The next big thing is already here.’”

He believes this speaks to exactly why companies are investing in hardware infrastructure for FPGA-based ASIC prototyping and all of the EDA tools to go around it. They need to innovate or they will not be able to keep up with the market.

This pressure to keep up is also why Xilinx continues to generate new design wins and new revenue in what would have traditionally have been an ASIC or ASSP play, whether it be in wired communications or wireless—one of our core business segments, Saban said.

“All of those comms customers make these kinds of decisions, and in that case they are using the FPGA for a different purpose. They are not using it for ASIC prototyping. They’re actually using it in a system where they would have in the past maybe considered building an ASIC for it,” he added.


The challenges to power optimization extend beyond just the device itself to the framework of how power is viewed with a long-range perspective. This is the job of the SoC master builder who not only must juggle a number of choices and pick the best path to implementation for a device, but also have the ability to plan for the future derivatives. Understanding the implementation options and manufacturing options will only get more complicated as designs dive below 20nm.

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