How to detect and correct reliability issues in advanced chip layouts.
With increasing design complexity and a heightened focus on reliability at all levels of integrated circuit (IC) design from intellectual property (IP) to full-chip, accurate and full verification coverage of the different reliability concerns within an IC design is essential. Designs containing multiple power domains add more complexity to reliability verification with the need to validate interactions between the different power domains. The Calibre PERC packaged checks flow with pre-coded checks lets designers select and combine cross-power-domain electrostatic discharge (ESD) protection, electrical overstress (EOS), and level-shifter detection checks for their multiple power domain designs without worrying about coding a complex setup. Using the Calibre PERC packaged checks flow, design teams can shorten the IC design verification cycle while safeguarding product reliability.
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