Validating DFT connections early and enabling a design agnostic custom methodology.
Whether you are a DFT engineer or a SoC designer, connectivity validation will no doubt be a top priority when taking steps to guarantee the functionality and reliability of your device. SoC designs continue to grow in both size and complexity to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution, the corresponding DFT logic required for manufacturing tests has also become more complex. Ever increasing transistor density, combined with a growing mix of both internally developed and third-party IP, presents multiple challenges related to validating DFT connections.
As hierarchical DFT flows become more popular, the use of signal connectivity checks and verification continues to grow. The technology is now also now being utilized by SoC designers who are reaping the benefits as part of full-chip integrations. Multi-die systems are also becoming more prevalent and this in turn is driving new requirements for greater assurance of proper interconnectivity and data integrity.
DFT connectivity checks are an essential part of modern semiconductor design and manufacturing and are becoming even more critical as more designs make the switch to multi-die technology. They are used to verify that the connections between various components or circuit elements within an IC or SoC are proper and correct. This means that devices can be successfully tested and diagnosed during the early design and production phases as well as throughout the silicon lifecycle.
Connectivity checks ensure that all components and signals within the chip can be accessed, observed, and controlled during testing. This is crucial for identifying and diagnosing defects or faults in the manufacturing process. They also enable fault detection and with isolating faults, that may occur during manufacturing. Without efficient connectivity checks it becomes very difficult to pinpoint the exact fault location. Other benefits of connectivity checks during the manufacturing process include quality assurance, cost savings in terms of test time and faster turn-around time.
Verifying that all interconnections are correct also helps to increase yield, leading to greater reliability and robustness. Connectivity checks also play a key role in debugging, making sure that the chip operates as originally intended. They also contribute to a more efficient and cost-effective testing process by reducing test time on the tester.
Design for testability is getting more challenging in terms of targeting complex fault models, achieving low DPPM and high coverage. As design sizes grow in complexity, the challenge to validate that auto-inserted test logic infrastructure has been implemented correctly is becoming more difficult. Ad-hoc methods like visual inspection, scripting, test benches for exercising test modes and other methods are very time consuming, particularly debugging the root cause when there is an issue. The root cause of most issues at SoC level, including simulation failures, is incorrect connectivity and/or proper setup control. Users need to detect and fix the DFT connectivity issues early in the design flow to make sure that there are no connectivity verification escapes causing ECOs close to tapeout.
Additional connectivity verification challenges occur when top-level IPs like embedded monitors, PLLs, BIST controllers, and eFuse are manually inserted. The generation and optimization of JTAG and the consequent hook up with test IP and test logic is also a manual process and as a result design change frequency is high. These multiple changes in specifications related to design and testability can result in thousands of top-level connections in a typical advanced node design as shown in figure 1. In some cases, manual top-level integration of blocks that have complex compressed cores takes place with pipeline flops also being added at the top level. To reduce debug turnaround time in ATPG DRC checks, running a quick check, at SoC for connectivity, could save time.
Fig. 1: DFT Connectivity verification challenges related to manual insertion of top-level IPs.
Some common examples of connectivity issues are highlighted in figure 2 and often involve illegal paths in different scenarios including back-to-back On-Chip Clock Controllers (OCCs), clocks feeding the wrong module or a MUX with the wrong select.
Fig. 2: Examples of illegal paths leading to DFT connectivity verification challenges.
Other important checks include one-to-one connection or point-to-point connection. For example, connectivity checks if node A is driven by node B. One-to-many connections: For example, connectivity linting checks if the memory shift_n pin is driven by the inverse of node A, where the start point is node A and the end points shift_n of memory (due to many memory instances in SoC). And lastly, many-to-many connections where checks are performed to make sure that the memory mem pin is driven by data registers, where the start points are the Data Register (with many instances in SoC) and the end points are the mem pin of memory (many memory instances in SoC).
A violation can occur due to incomplete or incorrect simulation conditions or incorrect design connectivity. These rules are used to check required or illegal value at given point, see figure 3.
Fig. 3: Value checks under different enabling conditions.
Connectivity exists between a source and a destination node, and therefore there is a possible path between the source and the destination. Combinational logic in between is allowed, as long as constants do not block the path. Direct connectivity exists between a source and a destination. In between the two nodes, there is nothing apart from buffers and inverters with no change to polarity. Enabled connectivity exists between a source and a destination. Any combinational logic in between is configured by constant propagation to allow only the selected path to propagate, as shown in figure 4.
Fig. 4: Point to point connectivity checks.
Most test logic is auto inserted as part of synthesis with functional regression being used to verify design in functional modes. But for the complex test modes (ATPG, MBIST etc.), ad-hoc methods could be used:
Customizable connectivity checks are a set of rules that are specific to a particular IC or SoC to allow it to be tested correctly. These customizable checks may include rules to verify that components like scan chains, boundary scan cells and flip flops within the design are connected properly to allow test signals can be applied and monitored. This customization enables the device to be tested during manufacturing. The types of checks and rules applied will vary depending on the overall complexity of the device itself, giving much greater levels of adaptability and flexibility.
Dynamic Defined Conditional Connectivity Macros (DDCCMs) are specific constructs used in the design process to control the connectivity and testability of certain components in ICs and SoCs as well as how signals are routed. They allow both DFT engineers and SoC designers to dynamically configure and control various testability and connectivity features based on specific environmental conditions or design requirements. As DDCCMs are dynamic and not static, it means their operating behaviour can be changed based on the requirements of the design itself. Their conditional characteristics mean that the rules are only triggered when certain conditions occur, or criteria are met.
This approach is based on creating connectivity solutions that are not specifically tied to a particular design and therefore can be applied to a much wider range of ICs and SoCs enabling greater levels of reusability, portability and scalability.
The ideal characteristics of an effective and robust DFT connectivity checking solution should help to identify the root cause for failures effectively and easily with false violations or noise minimized. It should also support regression so that the connectivity checks can be quickly performed with any ECO flow to validate that DFT connections are intact. Also, if the constraints are technology and design independent, they can be reused.
Validating DFT connections at SoC assembly and facilitating design agnostic custom methodology is a feature of Synopsys’ testability analysis solution, Synopsys TestMAX Advisor.
The technology enables usage at the RTL stage so issues can be identified and corrected early for maximum usefulness. Other valuable attributes of the technology include the ability to reuse checks across the design and provide a clear description of the root cause of the connectivity problem. While standalone signal connectivity checking is not replacing standard simulation-based verification, which could also find these issues, it is a complimentary ‘early warning’ verification.
TestMAX Advisor validates connectivity across hierarchies, checking both paths and values. This validation not only applies for test logic added at the SoC integration level but also for any logic not related to test. TestMAX Advisor addresses connectivity challenges such as back-to-back on-chip controllers (OCCs) that find no clock control connection. Examples of value checks include PLL resets or clock gating enable pins. Conditional checks are also supported, for example memory sleep controlled by pin at IP level. Connectivity validation can be performed either at RTL or gate-level netlists. Connectivity checks can also be used to create design-agnostic custom methodologies.
As well as the latest connectivity validation capabilities, Synopsys TestMAX Advisor also covers other areas of testability analysis:
Fig. 5: The feature set for a complete testability analysis solution.
DFT connectivity checks are now essential for ensuring the overall quality of cutting-edge technologies through efficient testing and accurate fault detection. They are a fundamental part of the design process, particularly in complex ICs and modern SoCs, where there are numerous interconnected components and signals as well as a mix of legacy and new IPs that have heterogeneous connectivity requirements. Properly verified connectivity is crucial for achieving high manufacturing yield and the long-term reliability of electronic products.
Connectivity checks were initially targeted for DFT teams. And now SoC design teams realize the advantages experienced by their DFT counterparts and are rapidly adopting connectivity checks.
You can learn more about validating DFT connections by registering for a new Synopsys webinar on November 28, 2023. The webinar will examine the main characteristics of effective and robust connectivity checks and cover topics including basic customizable connectivity checks, the use of dynamic defined conditional connectivity macros and showcase the latest Synopsys TestMAX Advisor GUI analysis and debug capabilities. To learn more about Synopsys TestMAX solutions, visit our website.
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