Cost Per Transistor Gets Fuzzier

By Ed Sperling
Cost per transistor always has been a major reason for chipmakers to migrate to the next process node. By shrinking transistors and adding more logic, performance usually gets a boost. Moreover, that usually provides enough engineering wiggle room to add some improvements in energy efficiency.

The basic assumption that you can double the number of transistors every 24 months, and at a minimum drop the cost per transistor at each new process node, is the main reason portable electronics are so affordable—and why they can offer better performance and energy efficiency than multimillion-dollar mainframes a couple decades ago. But cost per transistor is getting harder to measure. Just as semiconductors are becoming more complicated, so is the math required to actually determine how much each transistor will cost. There are even questions surfacing about whether this approach is even relevant anymore.

With a system on chip it is much more difficult to determine the overall cost per transistor. There are multiple logic systems and subsystems, arrays of black-box IP, and analog blocks that render standard digital metrics meaningless. Add to that double patterning at 20nm, 3D transistor structures, almost perpetual software updates, and extra testing along the way.

“The factors that affect the cost per die have not changed,” said Radhakrishnan Pasirajan, senior director of engineering at Open-Silicon. “But the real question is how long it takes to mature a process. It is validated over a period of time and the yield is improved.”

It’s too early to tell just how long it will take for advanced nodes to hit maturity. Double patterning already is well understood, but it still takes longer to do than single patterning. Moreover, many chipmakers have only been double patterning some of the metal layers but not all. At 14nm—the real 14nm, rather than the hybrid node that combines 20nm back end of line process technology with 14nm finFETs—more metal layers will require double patterning, and some will require triple or quadruple patterning. And with EUV lithography nowhere in sight to replace 193nm immersion technology, that will complicate things down even further.

What’s important to measure?
All of this impacts cost per die, and that cost needs to be looked at by market segment. In some markets, such as data centers or corporate networking, cost per transistor is almost meaningless because the systems for which these ICs are being designed cost tens of thousands to millions of dollars. In others, such as a developing market smart phone or tablet computer, fractions of pennies count.

“In high-performance computing and communication systems, companies are driven to use the most advanced process nodes to achieve their functional and throughput goals,” said Drew Wingard, chief technology officer at Sonics. “We’re seeing a trend that design work is switching from semiconductor companies back to the system companies—and the re-emergence of high-end ASIC companies to support them. This is because the unit volumes in these markets don’t lend themselves to the kinds of general standard-product SoCs that the semiconductor companies understand, especially given the high design costs.”

In the mobile consumer market, in contrast, the trend is for system companies to design their own SoCs.

“There are two factors at play,” Wingard said. “First, the semiconductor companies have effectively priced each other out of the market. It is awfully difficult to achieve the required profit margins when a company needs to spend upwards of $200 million to design an SoC that intends to sell for about $10, even in high volume. The semiconductor companies have failed to monetize the systems content that they’re required to provide in these SoCs and the supporting software. As a result, the semiconductor company is forced to overdesign the SoC to stretch the number of customers and sub-markets that it can support, making it less optimal for each end device it targets. This leads to the second factor: System companies believe that they can better optimize and differentiate their products by taking on the design task.”

So a $10 application processor, for example, may enable a $400 to $500 smart phone, and the systems vendor can amortize the design costs across the end device. It also can economize better because it can design in the exact features that are required. The result is a better user experience and a more efficient pricing structure.

There are other ways to impact the pricing per transistor, as well, but the measurements are less about cost per transistor than cost per die or per wafer.

“One way to prevent the cost of a die from going up is to add in complex power management schemes,” said Pranav Ashar, chief technology officer at Real Intent. “The problem is that simulation is incomplete, so you need more specialized tools to manage the complexity and control the design process so that the cost per die doesn’t go up.”

That’s easier said than done, however. Complexity is now multifaceted—some would characterize it more as hydra-headed—and things like clock domain crossing, electromigration and electrostatic discharge, which used to be a third-order effects, are now first-order effects.

“No one tapes out without clock domain crossing signoff or power management control and constraints management,” said Ashar. “In the past, most of the constraints management was in place and route. Now it’s moved up higher in the abstraction. We also have to synchronize probability models because all the margin is based on those models.”

Balancing act
What’s emerging is a view of design and manufacturing as intricately entwined and delicately balanced. Adding margin reduces performance and impacts the overall power budget and cost—it has a negative effect all three pieces of the area, power and performance equation—but that cost is balanced with potentially better yield and fewer physical effects to deal with.

“Any time you remove margin, you are at risk for yield-limiting problems,” said Tom Ferry, senior director of marketing for Synopsys’ Silicon Engineering Group. “So a via that uses less margin may be more susceptible to failure.”

That same balancing act applies to turnaround time and accuracy, as well. So while the tools may add to the initial cost, such as full lithography simulation or pattern matching, the alternative may be lower accuracy.

“What is clear is that the nature of yield is changing,” said Ferry. “We’ve moved from yield as a fab and process issue to more design-dependent issues. So what we’re finding is that just because one design works out fine, the next may have peculiarities because of the way it was laid out and the timing. In the past, that issue was more design independent. But the reason that issue shows up in the first place may be due to process, lithography, patterning, or maybe even timing.”

On top of that, the number of problems per node is increasing.

“We are slowly hitting the limits of physics,” said Open-Silicon’s Pasirajan. “It’s taking more time to stabilize designs and what are the best yield. We’re seeing more physical effects in the interconnects and with higher frequencies, which means you have to factor in distortion of the signal because that eventually affects reliability. So all of this takes longer. The mask is more expensive. You also need to add in more integration. IP is one of the major problems we’re facing now. Just because IP is available doesn’t guarantee it can me integrated. IP has to be tested in a particular configuration, and while you’re developing a chip an IP vendor may be developing a new version of that IP at the same time that you don’t know about. It should be co-developed with the chip or your final release of the chip is at risk.”

Still, that IP is a balance between time to market and cost, but if it causes a failure it also can end up costing more time—both in terms of trying to figure out what the problem is in the first place and then coming up with a solution. What does that mean for cost per transistor? So far, no one really knows.