Custom IC Design: They Call This Progress?

Integration of digital and analog blocks still problematic; different tools, different languages, different perspectives.


By Ed Sperling

For decades, analog and digital engineers have lived in completely separate worlds. The lines are blurring between those worlds, though, in complex SoCs. So far, the transition has been difficult, and most engineers predict it will get worse at future process nodes.

The basic problem is that each world has functioned independently of the other from the start. They use different tools, they work on different schedules and they generally think about problems from a different vantage point. There are some very good reasons for this. In the digital realm, designs typically last only a year or two. In pure analog, they can last a decade, with a major emphasis on having a specification that’s performance tuned to be just a notch better than the competition.

“These have been two very distinct markets,” said Ed Lechner, director of product marketing for custom design at Synopsys. “One is for standard analog parts, which is the world of Linear, Analog Devices and Fairchild. Their most popular node is 180nm and they tune for maximum performance. At the other end of the spectrum are the digital engineers who are working at 32nm and 45nm. They’re willing to forgo getting maximum performance for a quick and dirty solution so they can get the product out the door in time for the Christmas season.”

But pushing down to the leading edge of Moore’s Law also has opened up an enormous amount of real estate. That creates the opportunity to shrink a bill of materials, and therefore the cost, by combining functions that formerly were on multiple chips into a single chip. This is where analog meets digital, and the relationship—uneasy at a distance—is becoming even rockier when both functions are being forced to work in sync on the same development schedule.

Linda Fosler, marketing director in Mentor Graphics’ deep submicron division, just returned from a European tour where she met with 10 of Mentor’s top customers there. She said those companies want to be able to design mixed signal chips in the same time frame as digital chips and without having to boost the number of engineers to get the job done on schedule.

“One problem we’ve heard is that respins have made companies late to market, which is very costly to them,” Fosler said. “The problem is that the interface between the analog and digital blocks is not tested until the last minute because these teams aren’t working together. The industry needs to address implementation effects—basically the parasitics—of what affects the final qualification of silicon. It must be dealt with iteratively at the layout and schematic level, and built into the tools. We also have to build more intelligent manufacturing awareness into the tools.”

Failure to communicate

The fact that engineering teams are spread out around the globe doesn’t help matters. Even when analog and digital engineers are locked in the same building, they tend not to talk to each other. But none of the tools for developing chips have been constructed to deal with collaboration between teams, which is why most design is done in discrete units defined by the chip architects.

The problem is that in a mixed signal chip, it’s not just the teams that have to communicate. What they’re developing has to work well together, too.

“We’ve heard from some customers that to complete a chip in a compressed schedule, they tape out on tapeout day, whether they’ve finished the simulation or not,” said Bradley Geden, product marketing manager for AMS circuit simulation at Synopsys. “This is what causes re-spins. What’s needed is a formal methodology with sufficient verification and sufficient coverage in an AMS block.”

So far, that methodology doesn’t exist. Nevertheless, the amount of mixed signal content shows no sign of decreasing. Even with digital components there is growing analog content.

“As soon as you add analog onto a chip, the chance of respins increases three times,” said Mar Hershenson, vice president of product development in Magma’s custom design business unit. The schedule is more complex and the tools allow us to put more content on a chip. But they need to work much better. A lot of companies complain they don’t have enough analog designers, but the digital people and the analog people don’t speak the same language and they don’t have the same tools. When it comes time to integrate, that’s where the problem begins.”

Nevertheless, she said the real selling point for mixed signal chips is integration. The less work the customer has to do to integrate those functions, the more attractive a company’s technology looks.


Most tools vendors see mixed signal as an opportunity. They recognize that analog will never be completely automated because some functions will always be customized for a specific chip. But it can at least be enabled and integrated better into the complex design process that includes both digital and analog.

This becomes particularly important as analog engineers are forced to fit into digital design schedules. Getting a design out the door, relatively bug free and on schedule has been achievable so far primarily by ramping up the number of engineers working on those chips. There’s a bundle of money available to the tools vendors that can reduce that pain, and the race is already well under way.