Customer Perspective: STMicroelectronics

Second of two parts: Wide I/O, ecosystems, power, and faster software development will drive huge changes in SoCs over the next few years.


By Ed Sperling
Philippe Magarshack, group vice president for technology R&D at STMicroelectronics, sat down with Low-Power Engineering to talk about some of the fundamental changes ahead in how SoCs are designed, built, how they perform and what steps can be taken to speed time to market.

LPE: What do you see as the biggest changes ahead?
Magarshack: One is the sheer size of the ecosystem and the relationships you will need to have moving forward. We are already dealing with this at 28nm. At 20nm, we see this is as a tremendous challenge. We are not alone. The competition has to deal with this, as well. We have the size to justify moving to 20nm, and 14nm in the future. We also have a network of foundries, not only for manufacturing but also for process R&D, and we are able to do some of that process R&D internally. When you look at the holistic cocktail of components needed to move forward, this is very challenging. But we are also one of two players that can actually take advantage of that.

LPE: Who’s the other one?
Magarshack: Intel. Even though they are coming from the high-end microprocessor market, they are certainly very serious about moving toward systems on chip and lower power. They aren’t there in terms of low power, but they are very focused. There is also R&D among big established players.

LPE: Where does stacking of die fit in?
Magarshack: There is a lot of buzz about stacking of die and TSVs. We are not quite there. But the trend toward system-in-package, which may include 3D stacking or side-by-side or some other combination, is very strong. We are using that for our set-top box and digital products. We are concentrating the pure digital design on 28nm and using to our advantage lower cost and more efficient processes for all of the analog systems.

LPE: What node is the analog in?
Magarshack: It’s typically 65nm, moving into 40nm now. Over time we have perfected the ability to integrate two die together in a package, minimizing things like power and crosstalk. The overall system cost is not the only benefit at the end. In terms of program management and schedule, you concentrate your teams on the digital and making the analog IP work. We see this as a benefit in time to market. We also can swap the analog out without having to wait for the digital die. So while we don’t see a strong market case for 3D stacking, at least for the next two or three years, we do have the capability in-house, as well as with our foundry partners, to make this happen. We already have prototypes. The first products we see will be DRAM with wide I/O.

LPE: What’s the perceived benefit of system-in-package with wide I/O? Is it better power management, better utilization of cores, performance, or cost?
Magarshack: The cost is not a driver. At this point it will be neutral, at best. The number one benefit is the memory bandwidth. When you have intensively used CPU cores or graphics engines, they need to access 1,000 or 2,000 bits of memory. This is something enabled by wide I/O. And in terms of total system power, for the same quantity of data being transferred from the DRAM to the chip, the wide I/O drivers are much smaller. The distance is smaller so the overall power of the system is lower. That’s the other big advantage. One technical change that has not been addressed is that, as a consequence of this intense activity on the DRAM and the processing engine, you have a temperature elevation. Removing the heat is one of the big issues. We are working to simulate the heat effects and to have ways of dealing with it.

LPE: What’s new, though? We’ve had memory on the chip, on the board, and now we’re playing it somewhere in the middle.
Magarshack: We may be able to remove some levels of cache. That improves the system response in case of interrupts. The size of the DRAMs also is increasing at the level of Moore’s Law. We have not been able to take advantage of all these bits and DRAM except through the I/Os, so for me wide I/O is a potential architectural breakthrough. Within two or three years this will be on the table and it will be at the forefront of SoC technology.

LPE: What’s the big hurdle going forward? Is it the hardware or the software?
Magarshack: We have come a long way in optimizing pieces of the hardware and the software. There is still more that can and should be done in terms of validating the software before the hardware comes out. We also have come a long way in virtual prototyping where we can boot the operating system and debug the device drivers before we develop SystemC models for the IP, or a combination of hardware emulation of the other IPs. Once we get silicon, we can plug it in the board and boot the OS within hours, and have significant applications running within days. After that, applications can run in real time before we find problems that need to be fixed. But we can take advantage of the silicon as soon as it comes out and go into production soon afterward. We still have to wait between 6 and 12 months for software bring-up and testing of software in the customer’s environment. To me that has to be shortened even further.

LPE: Will 2.5D allow some of the software to be re-used, as well?
Magarshack: If you have an adequate digital chip and you need to add another interface, you may only have to touch one device driver.

LPE: Will this be available from other vendors or will it still be ST developing the software, hardware and IP in-house?
Magarshack: We do see this as a differentiation for us. We have applications ranging from GPS to set-top boxes and WiFi, and we are able to bring in the hardware as well as the software part. There are millions of lines of code developed for systems on chip. We do most of that internally, but we are looking for and finding external partners, as well, for things like device drivers. We also are looking at what open source can bring us. This is easing the burden of software development. But the integration goal is a differentiation, and we will not hand off this function to an outside partner.

LPE: Will you have a standardized way of building and packaging these kinds of chips?
Magarshack: Yes, and we are one of the few that have the breadth of applications from consumer to auto to wireless. We are taking the approach that business units within ST are exchanging IP, both hardware and software, among each other. We have IP in our GPS group and they are moving IP into wireless. WiFi expertise is moving toward automotive. We definitely are doing these exchanges. For this exchange to work, we are working on internal IP standards so you can plug it in and re-use it. We have the SPEAr (MPU) family, where we have processor cores and GPS or other modulator IP, encoders and decoders. This can use an undifferentiated block that can be configured by the customer. They can put their own proprietary IP or then can ask us to provide it.

LPE: So to some extent you’re breaking your products down as platforms and subsystems, as well as lots of other IP?
Magarshack: Yes, and this is not just the hardware IP. It’s hardware and software.

LPE: Is it a combination of cost and speed to market that’s driving this?
Magarshack: Time to market is the most important.

LPE: What happens to your ecosystem? Does it grow or shrink, and does it get tighter?
Magarshack: We tend to have deeper and stronger relationships with fewer partners. We have moved to become part of the Common Platform alliance. We work with IBM, as well as the foundries of silicon, in addition to our internal fabs. We have developed intense relationships with these companies. We also need to have a strong relationship with the back-end assembly partners. Each part of the supply chain has to be extremely reliable and committed and focused. We need tight delivery dates across the entire food chain.

LPE: Any changes in materials that will be used?
Magarshack: Right now we are moving forward with a differentiated approach. We are building on top of the bulk CMOS. At 28nm we are moving forward with fully depleted SOI. We believe this will bring a very strong advantage for us of higher performance at the same voltage or lower power. We are now moving to take advantage of this with our partners.