Delivering Breakthrough Performance And Power Efficiency With PCIe 6

PCI Express (PCIe) has been the backbone of high-speed data transfer in computing systems for nearly two decades. With each iteration, PCIe has not only increased data bandwidth but also introduced innovations aimed at enhancing power efficiency—a critical factor in today’s energy-conscious computing environment. PCIe 6 introduced significant technical improvements that optimize power consumption while doubling the performance over previous generation PCIe 5.

PCIe 6, released in January 2022, introduced a data transfer rate of 64 GT/s (gigatransfers per second), double that of its predecessor’s 32 GT/s. This increase translates to a potential 128 GB/s in each direction for a 16-lane (x16) configuration, facilitating faster data processing and reduced latency.

To achieve this leap in speed, PCIe 6 employs 4-level pulse-amplitude modulation (PAM4) encoding, which allows two bits to be transferred per signal. PAM4’s encoding of two bits per signal leads to a more efficient use of the available bandwidth and lower power consumption per bit.

However, given the lower margin between signal levels, PAM4’s higher bit error rate necessitates robust error correction mechanisms. PCIe 6 addresses this in the controller by implementing a lightweight Forward Error Correction (FEC) system, with minimal latency impact (around 2ns).  PCIe 6 also leverages a Cyclic Redundancy Check (CRC) to catch errors that may get past the FEC, and the combination of FEC and CRC ensures data integrity without significant overhead.

The FEC requires fixed-size packets, so PCIe 6 introduces FLIT mode, where packets are organized in Flow Control Units of fixed sizes, as opposed to variable sizes in past PCIe generations. FLIT mode also simplifies data management at the controller level and results in higher bandwidth efficiency, lower latency, and smaller controller footprint. With fixed-size packets, the framing of packets at the Physical Layer is no longer needed. FLIT encoding does away with the overhead of 128B/130B encoding and DLLP (Data Link Layer Packets) from previous PCIe specifications, resulting in a significantly higher TLP (Transaction Layer Packet) efficiency, especially for smaller packets. The FLITs for PCIe6 are 256-Byte packets comprising of 242 Bytes of payload, 8 Bytes of CRC and 6 Bytes of FEC.

In addition, PCIe 6 introduces advanced link training and equalization techniques that dynamically adjust the signaling parameters to optimize data transmission quality. By continuously adapting to the channel conditions, these techniques reduce the need for retransmissions and excessive error correction, thereby lowering the power consumption associated with maintaining reliable data links.

The PCIe 6 specification incorporates power-aware features that allow the hardware to make real-time decisions about power states based on workload demands. This dynamic power management ensures that components operate at optimal power levels, reducing energy consumption during periods of low activity without sacrificing performance when high throughput is required.

Specifically, PCIe 6’s L0p mode enables dynamic scaling of active lanes, reducing power consumption without the need for renegotiating the link width as was required in previous generations of PCIe. In PCIe 6, the link always trains at the highest possible width and can subsequently modulate its width depending on the workload requirements.

Next-generation PCIe 7, which uses PAM4 to push data rates to 128 GT/s, builds on these performance and power efficiency innovations debuted in PCIe 6. Whether PCIe 6 or 7, Rambus has a portfolio of digital controller, switch and retimer IP for your high-performance SoC designs. We supplement this offering with a suite of debug and test solutions, like the XpressAGENT add-on cores, that help customers speed their designs to market. With 35 years of high-speed signaling experience and hundreds of first-time-right PCIe design implementations, Rambus can help you realize the power and performance benefits of PCIe.

Links:

• PCIe 6.x Hardware Demonstration of L0P and FLIT Mode
• Rambus PCI Express IP Solutions