Design For Noise (DfN)

By Riko Radojcic and Yanfeng Li
Abstract: This white paper describes the typical characteristics of electrical noise, and summarizes the current standard practices for managing noise in semiconductor devices. The impact of the technology trends – and specifically CMOS scaling – on noise amplitude and circuit sensitivity to noise are presented, and the requirements for coping with this emerging concern – “Design for Noise” – are identified. A summary of the characteristics of available solutions for direct noise characterization compatible with statistical modeling and for volume process control for noise, is outlined.

I. Introduction: Design-for-Noise (DfN)
Design-for-Noise, much like Design-for-Manufacturability and other Dfx practices, is in many ways a new name for an old problem. However, all technology trends are turning what used to be a second order variable that was important only for specialty applications, into a primary concern that will impact mainstream products. This therefore requires development and deployment of a new methodology for managing noise effects – “Design for Noise”. Much as was the case with many of the DFM solutions, that ended up with OPC and RET practices deployed by the manufacturers, the DfN methodology proposed here focused on the manufacturing and characterization solutions, rather than developing radical new design practices. That it, it is proposed that a practical approach to managing noise in IC design is to enhance the SPICE-based methodologies developed over the last few decades, with better characterization, better models and better process control practices.

II. The Physics – What is Noise
Much has been written about the various types of noise in electronic devices, and their respective sources, and consequences. Table 1 is a summary of the typically cited categories of noise:

These noise phenomena are not new, have been studied for decades, and there is a set of pretty well established mathematical models that describe each of the mechanisms. Noise characterization, modeling and management techniques have been developed, and typical sensitivities of various device types (BJT, JFET, MOSFET..) are known. Mitigation circuit design practices are pretty well established, as well, especially with Big Analog design – things like DACs and ADCs that need to resolve a small voltage steps, or Filters and Amplifiers that need to resolve small signals from the background and/or the carrier.

For mainstream Semiconductor Device types, the most significant sources of noise are Thermal and Flicker noise. In addition, Shot and Burst noise are important for circuits that involve matching and/or small charges. In general, noise is classified and behaviorally modeled as “White Noise” (Thermal + Shot), with no frequency dependence, and “1/f Noise” (Flicker + Burst) with strong spectral dependence (sometimes also called Pink Noise).

III. Current Practices – What is Normally Done About Noise
Current standard practice for managing the effect of noise is basically a “Measure & Model” approach. That is, noise is characterized on selected sample of representative devices, and is then modelled within the standard device models, such as BSim or PSP models for MOSFETS or HiCUM or MEXTRAM models for BJT’s. This then allows designers to perform suitable SPICE simulations on their circuits to ensure adequate margins for the effects of noise.

Typically, noise characterization data is presented as a noise voltage (or current) density function vs frequency, as illustrated in the figure below. Note that measurement of noise calls for specialty equipment and custom test set up, in order to minimize the effects of both, internal (e.g. noise of the test equipment itself) as well as external noise (e.g. coupling within fixturing and cables, etc…). Thus, noise characterization tends to be quite involved, slow and painstaking, and is typically performed only as a part of the initial in-depth engineering device characterization.

“Corner Frequency”, as defined in the figure, is typically used as an overall figure of merit for noise associated with given device types or process technologies. Corner frequency for bipolar devices is of the order of 1 to 10 kHz (implying that 1/f noise component is low relative to the thermal noise component), vs 100 kHz to 1 MHz for MOSFETS (implying that 1/f noise component is more significant than the thermal noise). Devices built on III-V processes, such as gallium-arsenide FETs and indium- gallium-phosphorous heterojunction-bipolar transistors can have1/f corners in the region of 100 MHz – implying that 1/f noise dominates all other sources even though the noise magnitude can be very low.

Note that, the actual noise models used for SPICE simulation are very complex. Basically, a noise model must comprehend frequency exponent (slope of the 1/f region), bias dependence (intercept on x-axis of the 1/f region) and thermal dependence (intercept on y-axis of the flatband region). This is then integrated in the device model for the subthreshold, linear and saturation regions of device IV characteristics. Furthermore, noise – and especially the 1/f (flicker and burst) noise, being a result of defect and interface states in the band gap – is a direct function of a process technology and specific processing recipes. Noise hence varies with the manufacturing process, and potentially has something like ‘fast’ and ‘slow’ process dependency. This variability in noise, as well as the thermal and voltage dependencies, all need to be correlated to all other Process – Voltage – Temperature (PVT) sensitivities in the device model. Consequently, extracting and fitting device models with noise parameters involves very scary equations and is a complicated art typically best left to the device modeling experts.

Nevertheless, given suitable characterization and extraction, good device models nowadays typically do include noise, thereby allowing SPICE simulation of the effect of noise on a given circuit. However, since measuring noise and incorporating it within the standard device models is slow and challenging, device models and circuit designs are all typically margined up, to ensure good yield and performance across the entire PVT variability range. Relying on suitable excess margin to ensure yield and reliability, especially for parameters that are only indirectly controlled – such as noise – is time honored tradition that has served the industry very well, and is hence currently ubiquitously practiced with noise management and mitigation.

IV. The effect of Noise and Why Does Noise Matter
Fundamentally, noise represents an intrinsic limitation that dictates the minimum signal resolution of any electronic system, and therefore impacts most circuits – especially those that operate at the low voltage/current levels. As such noise is sort of analogous to temperature that represents the intrinsic limitation for operation at the high voltage/current end. The effect of noise depends on both the nature of the circuit and type of noise. Specific classic examples include:

• The resolution of an LNA such as used for the rf front end circuits is limited in the high frequency range by the white noise – Thermal and Shot noise. Clearly signals whose magnitude and spectral range is comparable to noise cannot be resolved.
• The low-end resolution for circuits that rely on matching of differential pairs – such as DAC and ADC converters – is determined by mismatch, which can ultimately be limited by the random nature of noise. Least Significant Bit (LSB) must be larger than the noise level, and in MOSFET implementations it is dominated by the Flicker noise.
• The minimum charge stored and resolved in memory bit cells – such as in Flash cells – or minimum differences in resistance – such as in PRAM or MRAM cells – is ultimately limited by noise. Clearly the sense signal from stored charge, or resistivity difference, must be larger than random noise floor, in order to manage the Bit Error Rate (BER).
• Similarly, memory cells that rely on matched transistor characteristics – such as Vth in SRAMs – can be disturbed by noise – and especially Burst (Random Telegraph Noise: RTN) noise – affecting yield and BER. The effect on the consequent design window is illustrated in the figure below:

RTN affects design window for SRAM cells.

• The jitter of clocks in digital systems is affected by noise since the clock PLL circuits are driven by the Voltage Controlled Oscillators (VCO). Flicker noise in transistors is the main cause of phase noise for a VCO oscillator of the phase lock loop implemented in CMOS.

1/f noise can be up-converted and contributes to phase noise of a VCO

• Similarly, the performance of many sensors used in modern systems – such as CMOS Image Sensors, or various MEMS devices – are equally limited by various types of noise.

That is, noise is one of the fundamental limits for most devices, and as such, it is a key constraint for electronic design. It is not necessarily a new concern, especially for the analog circuitry dealing with low level signals, but it is creeping into the mainstream designs and is becoming a major constraint for digital processing and storage portions of electronic systems, as well.

Normal design techniques for managing noise effects boil down to “Filter and Amplify” approaches. Basically, noise is minimized in the spectral range that is relevant for a given circuit by use of suitable filtering techniques, and/or the intended signal is amplified without corresponding amplification of the noise signal. Clearly there are limits to these approaches, since any additional circuitry that could be used to filter noise also introduces incremental noise sources and come at a cost of Si area and/or performance, so that the problem cannot be entirely eliminated. Ultimately the amplitude of the intended signal must be above the expected noise level. Therefore, clearly, noise must be fully characterized and well controlled in order to enable robust design of advanced chips and systems.

V. Technology Trends – Where are we Going
Characterizing and managing noise is a growing problem because the technology trends are all conspiring to exacerbate the amplitude and the effects of noise in most device types and circuit designs. Therefore, in order to keep pace with the evolving technology trends, traditional practices for modeling, managing and mitigating the effect of noise currently used in the industry need to be revised and upgraded.

Technology trends that directly impact noise, and that are intrinsically and directly associated with the usual CMOS scaling, include:

• Scaling of CMOS devices naturally makes the effect of noise – and especially 1/f noise – worse. Fundamentally, flicker noise is empirically modeled as an inverse function of device area, and can be shown to be: V² = K/[(f)*(L*W*C^ox)], where K is the process-dependent constant, f is frequency, C^ox is the oxide capacitance in MOSFET devices, W and L are channel width and length respectively. That is, device scaling reduces the total device currents, and therefore makes Flicker noise more significant.
• Reducing operating voltages, associated with scaling, naturally makes the effect of noise – and especially the Burst (RTN) noise – worse. It is clear that with the reduced Vdd, the effect of Burst noise on, for example, the variability of Vth, and stability of the SRAM cells, becomes more significant.
• Reducing operating margins, associated with scaling, naturally makes the effect of all sources of variability more significant. Thus, just like the intrinsic variability in manufacturing processes, including even the very subtle phenomena such as Random Dopant Fluctuations (RDF) and Line Edge Roughness (LER), etc.. have major impact on parametric yield, so do all types of noise. Furthermore, the distribution of noise amplitude across the process spectrum becomes more significant, with considerable spread between the worst case and best case noise, as illustrated in the figure below:

Note that the worst/best case does not necessarily correlate to the normal slow/fast device corners, since noise – and especially 1/f noise – is driven by the interface states and/or traps in the band gap, rather than the usual primary L, W, Vth, u, etc …. parameters. Thus, the impact of noise and its variability is two-fold. That is, manufacturing process variability results in variability in relative sensitivity to noise, derived from the variation in primary device characteristics (Idd, Vgs, Vth, etc..), as well as in variability in actual absolute amplitude of noise, coming from variation in the secondary device characteristics, such as trap and surface state density. Note that these are not necessarily correlated.

Furthermore, second order phenomena that are indirectly related to scaling also tend to exacerbate the noise and noise management challenges. Consider for example:

• Increasing power and power density in scaled devices naturally leads to higher operating temperatures and greater temperature gradients across a die – with obvious negative effect on noise, and especially thermal and shot noise. Furthermore, a larger temperature gradients across a die necessarily result in increased across-chip noise variation – a factor that is normally not comprehended within the current SPICE simulation practices.
• Increasing impact of mechanical stress on device performance – either via intentional strain engineering (e.g. SiGe channel), or via unintentional phenomena such as the various Chip-Package- Interactions (CPI) – is likely to directly affect noise, and noise variability. Since stress-strain phenomena have a direct impact on Si crystal symmetry, as demonstrated by the stress driven variation in carrier mobility (described by the Piezoelectric coefficients), it is likely that these phenomena will also affect the distribution of trap density and trap energy levels – — and hence will have a direct and potentially significant effect on 1/f noise.

Finally, it is also quite conceivable that various trends in process and design technologies can end up having unintended impact on noise and noise sensitivity – neither one of which are directly measured and/or controlled in volume production. Consider for example:

• The backside preparation process – normally a step that has secondary impact on any IC care-about – is known to directly drive the backside surface trap type and density. It can be expected that the reduction of die thickness – nowadays as low as few 10’s of um’s for mobile and wearable applications and well below the nominal carrier diffusion lengths – brings this noise generating surface close to the active face of the die. Thus, it is conceivable that backside processing and die thickness can have an unintended impact on the effective noise experienced by the active devices.
• The new so called ‘More than Moore’ technologies that use 2.5D (side-by-side) or 3D (die stacked on top of each other) integration of like (homogenous) or different (heterogenous) die, introduce new features in Si – such as Through Si Vias (TSV) or backside metallization and uBumps. These features are also new sources of noise – either through conventional means (e.g TSV’s are effectively a large MOS capacitor that can inject a parasitic signal into the substrate and couple to active devices) or through unintended means (e.g. surface states on the TSV-Si interface may be a significant source of noise).
• The on-die thermal hot spots, caused by the high-power density associated with high performance processors used in modern SoC’s, are managed by dynamic throttling of performance through one of the standard DVfS (Dynamic Voltage and/or frequency Scaling) techniques. This requires use of on-chip temperature sensors, with the associated DAC and signal processing circuitry. These circuits are directly impacted by noise, and local noise variability may well affect their margin – ultimately impacting product yield, performance and/or reliability.

That is, it is clear that all the technology trends not only erode the margins to noise, but also exacerbate the noise itself. This would then imply that robust circuit design practices would favor use of larger margins to mitigate noise effects. However, all technical and economic pressures favor reduction of direct and indirect costs associated with excess margin – either in form of Si die area or power- performance. Thus, there is a contradiction between the need for excess margin to ensure yield, and need for minimized cost and maximized power-performance. This implies that as noise becomes more significant, there is a new tradeoff that requires optimization – Design for Noise – to identify and design to a ‘sweet spot’ between noise margin and most cost-effective Si utilization.However, identifying and selecting that ‘sweet spot’ also requires access to much better information about noise – to avoid the risk of either using excess margin and wasting Si area and/or performance, or using too little margin and compromising yield, and potentially product quality and reliability. That is, the current typical practice of characterizing noise and building nominal noise models during engineering development, and then relying on SPICE simulation to mitigate any product level noise effects, are running out of steam. This is especially so because noise sources are in fact quite poorly correlated to the typical metrics used to control the manufacturing processes – such as IDsat, IDlin, Vth, etc… That is, noise is expected to vary with wafer-to-wafer or lot-to-lot statistics, and may well drift during process life. Hence, noise – an emerging primary variable – should be measured explicitly and controlled directly; during technology development, during product characterization and debug, and during volume manufacturing. Furthermore, noise should be treated as a statistical variable, and as such measured on a statistically significant sample, and described either with corner models or statistical models.

It therefore follows that the traditional practices used for noise characterization and management should be upgraded – to enable rapid, easy noise measurements that are statistically representative and that are compatible with laboratory environment for detailed device characterization, engineering test environment for product debug, and test floor environment for process control in volume manufacturing.

VI. a Solution – Noise Characterization and Test
So, given that a new approach is required – what should it be? Some thoughts:

• Methodology for direct measurement of noise, rather than an inferred one – since noise is not well correlated to any of the standard basic technology metrics – is required. This then dictates a need for instrumentation with resolution and accuracy that is good enough for direct noise measurement.
• Methodologies for noise measurement that can be easily integrated not only with device engineering lab environment, but also with product test environment, as well as manufacturing WAT test environment, are required. This then dictates a need for suitable noise measurement ‘modules’ that can plug-and-play with the various typical types of test equipment and that are compatible with wafer probers.

Noise measurement methodologies that are fast enough to enable statistically valid characterization during engineering development phase and/or are compatible with product test and process control in volume manufacturing phase, are required. This then dictates the need for faster sampling and data crunching – without compromising accuracy.

Fortunately, as is often the case in our industry, practical and economic solutions that meet these requirements are emerging. These solutions can be deployed not only to enhance noise characterization within the current realm of engineering labs and deep modeling gurus, but also to bring noise characterization into environments that are compatible with volume manufacturing test, including the associated set-up, throughput and economic constraints. Specific attributes that have been demonstrated include:

• Hi Resolution & Accuracy: instrumentation that has resolution as low as <10-29A2/Hz, is now available. This enables direct measurement of even the noise floor of many sensor applications, such as MEMs, photo diodes, etc, and/or measurements of true DUT current down to pA’s, required for noise characterization of analog circuits in threshold and sub-threshold range. In addition, a very broad spectral range enabled by suitable SMU architecture that does not use a load resistor has been demonstrated. Figure below illustrates these resolution and spectral response characteristics:
  
• Self-Contained Modular Design: noise measurement platforms that includes super low noise SMU, multiple LNAs, a dynamic signal analyzer and PC based controller, all integrated with noise data analyses and modeling software, and therefore enabling easy integration with the existing lab and test floor set ups, have been demonstrated. In addition, the system includes innovative “self-adjust” noise cancellation mechanism and automatic LNA selection algorithm that ensures the hardware is ready to plug & play in any environment. Furthermore, the system is readily compatible with multi-die/multi- wafer testing and supports both standard DC and G-S-G probes, often required to manage oscillations in high res measurements.
• Speed: a 10-50X increase in measurement speed, relative to the existing methodologies, that enables direct noise measurements in seconds – without compromising accuracy and bandwidth – and that therefore makes statistical noise characterization and noise WAT testing economically viable, is available. This speed-up is derived from use of new hardware architecture and proprietary Artificial Intelligence (AI) algorithms that manage the in-measurement integration times, as well as advanced software for data manipulation and presentation.

Thus, direct and rapid measurement of all sorts of noise is practical and can be deployed in engineering labs for better statistical models, and in manufacturing test facilities, for better noise sensitive process control. Enhanced lab noise characterization enables extraction of statistically valid device models, which, in turn, enable accurate SPICE circuit simulation. Enhanced process control for noise ensures that the process in volume production does not drift from the process characteristics that were modeled. Better Models + Better Process Control enables designers to design with confidence to minimum noise margins appropriate for a given product. The ability to optimize noise margin with confidence is then the core of the proposed Design-for-Noise (DfN) practice – applicable and practical for even the most aggressive products targeting most advanced technology nodes.