Design For Power

Just looking at the design from the top down or the bottom up doesn’t work. Welcome to the new, improved team approach.

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By Ed Sperling
Figuring out a single power budget and mapping out what has become known as holistic power intent for an SoC sounds great on paper, but reality has turned out to be somewhat different.

While system architects still call the shots on how a chip is designed, there is a lot more information flowing in all directions further down the design chain these days. Unlike functionality, which can largely be set by a marketing department, power doesn’t always behave in predictable ways. And no matter how much progress is made on tools, gaps remain.

The challenge is bridging a high-level of abstraction, where the biggest dent can be made in an SoC’s overall power budget, with the back end of the flow, where measurements are accurate but it’s more difficult to make changes. Yet it’s precisely at the back end where problems really show up.

“The gate-level power analysis is much more accurate, but it’s too little too late,” said David “Woody” Norwood, principal applications engineer at Apache Design. “We’re finding power bugs that are logically functionally correct but which waste power.”

Norwood compared it to the New York skyline. When all the lights are on you can see where the power is going, and when all the lights are off it looks dark. But close in on the skyline and you’ll find not all the lights are off or on.

“Big companies are trying to stay within a 15% to 20% error margin for RTL, and some customers are even looking to move that up to 10%,” he said. But design for power isn’t always so predictable.

Opening up communications
One way to deal with power issues is to open up communication across groups that historically have functioned independently. At the place and route level, for example, the architecture is already set in stone. But talking to other teams—particularly software developers—can go a long way toward resolving power issues and preventing others.

“You can do a lot for power optimization in synthesis and place and route because you know the exact power numbers based on capacitance extraction,” said Arvind Narayanan, product marketing manager in Mentor Graphics’ place and route group. “If you’re doing a chip with four power domains you have to stick with those four domains even though you find you may only need three. But you can still have in impact on synthesis, floor planning, clock trees and software. We provide a lot of feedback to the software teams, which can still make changes that are comprehensive.”

This is a new communication channel for power. While there has been regular dialog between software and hardware design teams over performance and timing, power is a relatively new area for discussion. At least part of that is driven by the need for sticking within the power budget, which affects hardware and software, but part of it also due to the fact that hardware teams are now responsible for more of the software content. Still, power may be the glue to bring these two worlds together.

“The missing piece today is the link between the hardware and software,” said Ghislain Kaiser, CEO of Docea Power. “As an industry we have put more focus on the hardware, but with things like MIPI we’re starting to see the same issues coming up. One issue is how to make software companies participate in standardization. What’s becoming clear is that software companies now understand they need to optimize both hardware and software. But there are still many obstacles to making this work. These are not the same cultures and the way they purchase tools are different.”

Establishing feedback loops
Figuring out a common lexicon may be step one. While many people use power and energy interchangeably, there are different time windows for each. Power requires a narrow window because it can create thermal issues in an IC, while energy is more focused on how efficiently a design works and how long the battery lasts—as well as how it’s actually used.

“You have to be very clear about the design decisions you’re trying to solve and the needs to make those decisions,” said Pete Hardee, marketing director at Cadence. “The key limitation in all of this is real activity. Right now there are no ESL power modeling standards and there is a lot of confusion about what’s the system level. What is clear is that one size doesn’t fit all and models alone are not very useful without real activity data.”

He said that for power optimization there are a variety of techniques available such as clock gating, multi-voltage optimization and area/power performance, while there also are macro-architectural techniques available such as voltage islands, power shutoff, dynamic voltage frequency scaling, power shutoff and substrate biasing. But applying those requires a give and take between accuracy and high-level design.

That seems to be the general consensus among chipmakers, as well. Arif Rahman, IC design manager at Altera, said there needs to be a top-down and a bottom-up approach driven by good communication. This is particularly tricky in an FPGA, because programmability can radically change the way a chip is used.

“The same designs can end up with completely different use cases,” said Rahman. “Mixing custom plus standard designs is much more challenging.”

Converging approaches
The big challenge in a complex IC when it comes to power is to comprehend all of the pieces and the impact of one on the other. This is well beyond the the system architect at a high level, or engineers at the back end of the flow. Each of them understands pieces and can identify problems on their side, but there are many more issues that erupt before tapeout and even after a chip is in production and in a consumer’s hands.

“The tools should lead you to the right answer,” said Mike Gianfagna, vice president of marketing at Atrenta. “You start at a high level, add in as much data as you can, and as you move toward tapeout you want vectors that are convergent. But along the way you need to refine that to the point where you get to your target.”

That constant refinement, including more and more elements of the design, is what ultimately will produce a chip with fewer power surprises. And the only way to get there is with all the tools, the data—and better communication among more people working on a design.