Reduce over-design and determine exact margins with high-fidelity full-chip ESD verification.
Electrostatic discharge (ESD) is a major reliability concern for modern ICs. Ensuring the robustness of ICs in an ESD event by providing adequate ESD protection is proving to be a major challenge for IC designers due to factors such as shrinking of the design features, reduction in gate oxide thickness, increase in the contact and interconnect resistance and an increase in the overall design complexity. As designers push the boundaries of power, performance and area targets (PPA), it has become more important to avoid over-design of ESD protection circuitry. Designers must know the precise design margins provided by the ESD protection circuits, which is often prohibitive using traditional ESD verification approaches. Newer design tools can help designers determine the ESD margins with high fidelity, which reduces over-design. [1, 2]
Designers insert various ESD protection structures or devices inside ICs to alleviate the problems caused by ESD events. These structures shunt the high ESD current away from the functional blocks, preventing damage to the devices.
To ensure that these structures provide an effective shunt path for current to flow through, foundries set resistance limits or budgets for the ESD path. Designers can compare resistance values obtained by running a static check engine with the limits set by the foundry. If the path resistance obtained from the static checking engine is within the foundry limit or specification, then the design or IP is considered to pass the ESD check. In most scenarios, running static checking for ESD sign-off is a highly recommended and proven solution, but it does have some limitations. For instance, static ESD checking does not capture the exact triggering of ESD clamps in the case of a distributed ESD clamp placement scheme. It can also miss scenarios such as multiple fingers of a large ESD device turning on in staggered fashion. Assuming all devices are ON is very risky.
Foundries mitigate the probability of ESD risk by setting conservative limits for maximum allowed resistance for ESD paths. This technique typically results in over-design, increasing the chip area or implementation of these ESD protection structures at the expense of functional IP. Over-designing ESD protection also degrades performance and has a detrimental impact on the signal-to-noise ratio (SNR). Hence designers must complement the static checks approach with a solution that can help them determine the exact ESD margin on devices with high fidelity.
One way to improve fidelity is to run transient simulation at cell or block levels. To circumvent tool capacity issues while attempting to run transient simulation at the full-chip level, designers approximate or manually calculate the parasitics at higher levels of design hierarchy (figure 1). But manual processes are inherently error-prone, and there is always the risk of accidentally excluding necessary IP from the schematic. It takes weeks of effort and multiple iterations to construct these circuits and ensure that all the discharge paths are included.
Fig. 1: Different steps of a manual ESD verification approach.
To overcome the challenges highlighted above, designers can use newer technology for signoff-quality full-chip ESD verification which combines the context-aware reliability verification with SPICE simulation.
Context-aware SPICE simulation leverages the reliability verification tool’s knowledge of specific circuit topologies along with the layout geometries to retain only the portion of the design that is relevant for ESD simulation. This relevant portion of the design is transformed into a netlist suitable for transient ESD simulation.
Designers can use several different use models for this flow depending on what problem needs to be solved.
In the first use model, designers can identify if the devices are at risk of breakdown due to an ESD event if certain ESD discharge paths fail to meet the foundry-specified resistance criteria. In this case, designers can set up and run the foundry P2P deck and instruct the software to launch the flow on failing paths. Post execution, the software generates a detailed report highlighting any devices that exceed the voltage breakdown limit. If no devices are at risk, designers can request a waiver from foundry. If any devices are at risk, designers must fix the design.
A second use model is when designers want to evaluate the ESD margins for their design. In this case, designers can specify the top-level IO pins corresponding to paths that they are interested in simulating. The software will then perform automatic context-aware identification and detection of necessary circuits and layout shapes and execute SPICE simulation. Once the simulation finishes, designers get a report on various device voltages and the corresponding voltage breakdown limit, which allows designers to make smarter choices about reducing or trimming ESD protection circuitry in targeted areas of the chip.
The context-aware SPICE solution generates detailed and comprehensive reports and waveforms highlighting the problem areas on the chip. Designers can take advantage of the sophisticated debugging capabilities available inside the Calibre RVE interface to identify issues such as missing or inadequate vias or power grid straps.
The novel context-aware SPICE technology described here combines the context-aware reliability verification software and SPICE simulation technologies to deliver a groundbreaking approach to solving the problem of full-chip ESD verification while ensuring fidelity of ESD analysis. This technology provides the framework to help users achieve their ESD verification goals while increasing user productivity and reducing turnaround time through targeted simulation and state-of-the-art debug capabilities, thereby ensuring a shorter ESD verification cycle and optimally designed ESD protection.
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply