Challenges and troubleshooting employed to design a 2048-chiplet, 14,336-core waferscale processor system.
Abstract
“Waferscale processor systems can provide the large number of cores, and memory bandwidth required by today’s highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based architecture where pre-tested chiplets are integrated on a passive silicon-interconnect wafer. This technology allows heterogeneous integration and can provide significant performance and cost benefits. However, designing such a system has several challenges such as power delivery, clock distribution, waferscale-network design, design for testability and fault-tolerance. In this work, we discuss these challenges and the solutions we employed to design a 2048-chiplet, 14,336-core waferscale processor system.”
Find the technical paper here or here (IEEE Xplore). Published Dec. 2021.
S. Pal et al., “Designing a 2048-Chiplet, 14336-Core Waferscale Processor,” 2021 58th ACM/IEEE Design Automation Conference (DAC), 2021, pp. 1183-1188, doi: 10.1109/DAC18074.2021.9586194.
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