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WHITEPAPERS

Designing Application-Specific Processors for Wireless 5G SoCs

Heterogeneous ASIP cores are proving to be a feasible solution to meet the performance-intensive demands of 5G standards.

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Traditional architectures for wireless baseband applications are no longer adequate for recent and next-generation modem standards. Supporting complex and still evolving standards like 5G in a single modem is only possible by using SDR techniques, which place increasing demands on performance and power consumption on the SoC.

ASIP architectures enable full customization of a processor, which allows design teams to better optimize their SoCs. The use of multiple, heterogeneous ASIP cores is proving to be a feasible solution to meet the performance-intensive demands of standards like 5G. ASIPs achieve better power efficiency compared to general-purpose DSPs and are more flexible thanks to their inherent programmability compared to hardwired datapaths. Tool-based ASIP design methodologies automate the generation of the software tool chain, including an optimizing software compiler, and the generation of RTL for ASIC and FPGA implementation, which enables rapid architecture exploration (compiler-in-the-loop™) and trade-off analysis between performance, power and area (synthesis-in-the-loop™).

Read this white paper to learn how design teams using Synopsys’ ASIP Designer™ tool to tackle advanced wireless baseband designs for 5G mobile and base station applications are benefiting from its ease of use, higher levels of productivity, and predictable results.

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