System-Level Design

Designing with FinFETs: The Opportunities and the Challenges

Getting ready for 3D transistors isn’t as simple as it sounds, and the impact on the design flow can be significant.


With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar CMOS technology as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic power, intra-die variability, and retention voltage for SRAMs.

While a superficial view of the custom design flow, particularly with regard to design implementation steps, might suggest that the transition from planar FET to FinFET will be seamless and transparent to the designer, the impact of the FinFET device on the design flow can be quite significant. To learn more, click here.

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