Research paper titled “Data-Driven Offline Optimization For Architecting Hardware Accelerators” by researchers at Google Research and UC Berkeley.
Abstract
“Industry has gradually moved towards application-specific hardware accelerators in order to attain higher efficiency. While such a paradigm shift is already starting to show promising results, designers need to spend considerable manual effort and perform a large number of time-consuming simulations to find accelerators that can accelerate multiple target applications while obeying design constraints. Moreover, such a “simulation-driven” approach must be re-run from scratch every time the set of target applications or design constraints change. An alternative paradigm is to use a “data-driven”, offline approach that utilizes logged simulation data, to architect hardware accelerators, without needing any form of simulations. Such an approach not only alleviates the need to run time-consuming simulation, but also enables data reuse and applies even when set of target applications changes. In this paper, we develop such a data-driven offline optimization method for designing hardware accelerators, dubbed PRIME, that enjoys all of these properties. Our approach learns a conservative, robust estimate of the desired cost function, utilizes infeasible points, and optimizes the design against this estimate without any additional simulator queries during optimization. PRIME architects accelerators — tailored towards both single and multiple applications — improving performance upon state-of-the-art simulation-driven methods by about 1.54x and 1.20x, while considerably reducing the required total simulation time by 93% and 99%, respectively. In addition, PRIME also architects effective accelerators for unseen applications in a zero-shot setting, outperforming simulation-based methods by 1.26x.”
Find the technical paper here. Published as a conference paper at ICLR 2022.
Kumar, A., Yazdanbakhsh, A., Hashemi, M., Swersky, K., & Levine, S. (2021). Data-Driven Offline Optimization For Architecting Hardware Accelerators. arXiv preprint arXiv:2110.11346v3.
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