eFPGA: Think Differently & Experiment

New technologies are never overnight successes and usually develop in new applications.

Arm and other embedded processors today are a huge success and pervasive in almost all chips. It took Arm more than five years to win the first five customers. The first applications were not competitive with Intel’s PC dominance but instead filled needs in emerging applications such as mobile phones and music players, which have grown to become more important than the PC.

Rambus and derivative DDRx memory interfaces were originally viewed as more performance than anyone would ever need and too risky to make work in volume and cost-effectively. Surprisingly, the first multi-million unit product for Rambus was not a supercomputer as expected but a toy, the Nintendo 64, with, at that time, mind-blowing 3D real time graphics at a very competitive price.

Flash memories struggled for years to find markets then took off when emerging digital cameras and digital music players needed a low power, non-volatile memory. Today, flash rivals DRAM.

eFPGA is in its early days but is now starting to take off. eFPGA is not competitive with FPGA. eFPGA instead is enabling new applications and new architectures that will in time result in it being a technology that could be as pervasive as embedded processors now are.

The early adopters of eFPGA are doing two things differently. We see this because we are working closely with them. Most of what they are doing is yet unannounced, but it’s coming.

First, they think differently
Most customers approach eFPGA thinking about it like a co-coupled FPGA or a replacement for an existing ASIC block: they try to put in too much and they don’t think about architecting things differently. The early adopters of eFPGA are not thinking about cost reducing an existing system, and they are not worried about adding silicon area that lowers margins. Don’t misunderstand, they are not risk takers: they carefully evaluate and think through things, but they are architecting their solutions to solve critical problems that they have in innovative ways.

First, early adopters often realize that the best solution is not one big block of eFPGA but, instead, multiple blocks of different size doing different functions. And they work the architecture to hard-wire everything that does not need to be in eFPGA to minimize the size of the eFPGA to only that which must be reconfigurable.

The cost of eFPGA is that it is much larger than hardwired for the same RTL. The benefit is that it is changeable. They find applications where the benefits outweigh the costs:

1. They can design one chip that, with eFPGA, is now flexible enough to be used in 3-5 applications, instead of needing to do 3-5 different chips and masks if they had done fully hard-wired designs.
2. They can design chips where features that are in flux at tape-out can be resolved later in the design cycle, where algorithms are evolving rapidly so the chips can be updated when they do, and where protocols change unpredictably so chips don’t have to be replaced in system and in the data center when they do.

The net result is they find eFPGA improves their ROI and utilization of their design resources. After doing one chip, they generally think of more and better ways to use eFPGA in following chips.

There are companies now who have fabricated multiple chips with eFPGA and plan to use eFPGA routinely going forward.

Second, they experiment
If they are worried about risk or worried about how actual silicon will perform when simulations get too complex, they try something rather than doing nothing.

Many companies who get started with eFPGA do so first with an evaluation chip. Not a test chip, like Flex Logix already does, that validates the eFPGA core. But a chip with eFPGA that implements most or all of the actual features they want in a real product. This way, they work through the full hardware and software design flow and can see when they get back silicon and build systems if there are any issues or if they can “green light” eFPGA for production uses by all the business units in the company.

The HiPer consortium in Israel is doing this now with a TSMC 16FFC evaluation chip that will evaluate specific use cases of interest to companies including Mellanox, Satixfy, AutoTalks and DSP Group.

SiFive is enabling their customers to experiment without having to be chip designers by offering customizable RISC-V platform chips in TSMC28HPC, where customers will be able to specify one of several different eFPGA sizes for accelerator and I/O interfacing. SiFive’s evaluation platform chip is expected to tape out this year with evaluation boards shortly after, with eFPGA.

eFPGA is taking off
Flex Logix has announced 5 customers and has more. There are numerous other eFPGA companies and they likely have some customers as well. Sandia National Labs at GOMAC in March 2018 is presenting a paper on their eFPGA capability in their 180nm ASICs using Flex Logix EFLX for the US Defense community. Now that the first customers are moving into intial production, we see the pace of evaluation and design consideration picking up substantially.

Soon, the greatest risk for customers considering eFPGA won’t be starting too early but waiting too long.