Electronic System Design In 2015: Busting Through Bottlenecks

What really happened in 2014 and what it means for the future of chip design.

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It’s December, and that means it’s time to review what just happened in electronics design in the hopes that it will help light a path into the New Year. To simplify a year’s work in a global, sophisticated, ever-changing industry, you could say 2014 hinged on to two main tipping points:

  1. The marriage of EDA and IP was consummated.
  2. The road to the future forked.

Let’s look at #1 first. We’ve known that increasing design complexity, laws of physics, market demands and delivery pressures for years have weighed heavily on engineering teams. Old, partitioned ways of designing are being remolded because they have to if we were to keep up the productivity pace.

Relentless Reassessment
This has meant a constant reassessment of what design automation is. Venture capitalist and industry luminary Lucio Lanza, whom I interviewed in November, has a particularly elegant way of describing things:

“EDA has to understand that the challenge is to allow the design of new systems at the price and within a time span that is constant or shrinking. Our responsibility as a design automation community is to keep redefining ourselves by finding out what is the new bottleneck. Our responsibility, our challenge is to remove that bottleneck.”

It has taken some time, but EDA and IP — once partitioned — have coalesced in the service of bottleneck busting. In other words, the marriage that started out cautiously some years ago is now consummated.

This has occurred in the service of at least two bottlenecks. First is the persistent time-to-market pressure. Second is the value of integration where power, performance and area can be optimized with, among other things, deft use of IP.

Design IP — especially for new nodes — is becoming a critical component to early program decisions. We see an expanded “co-optimization” (yes, a marketing word) for new node enablement that includes key processor IP as well as critical mixed-signal IP.

At the same time, design is moving “left.” The shift left means everything that was done “later” in the design flow must now start “earlier” (e.g., software development begins before hardware is completed). Software development needs to begin early enough to contemplate hardware changes (i.e., hardware optimization and hardware dependent software optimization), while at the other end of the spectrum we see very early collaboration between the foundry, EDA tool makers and IP suppliers to co-optimize (there’s that word again) the overall enablement offering to maximize the value proposition of the new node.

“Shift left” consequences include the need for faster subsystem integration and assembly along with retargeting of existing subsystems, prototyping of new ones, along with performance, power and area (PPA) analysis. This is enabling improved architecture performance and target feasibility analyses across the system design spectrum.

Roads More Traveled
Now to #2, the fork in the road. This is not a particularly new phenomenon, but the respective paths have become much clearer in 2014. The costs and benefits of advanced nodes (16nm, 10nm, 7nm) accrue to fewer (and larger) companies, but the payoffs are enormous. So advanced node development forges on.

At the same time, the flowering of the Internet of Things market (with its vast potential volumes and low-cost requirements) means a much more extended life and value for nodes at 28nm and above. Indeed, the research firm IBS has shown data that indicates design starts at 45nm and below will continue to grow at a healthy pace. The data also shows that nodes from 65nm and larger will continue to comprise a strong majority of the overall starts.

This doesn’t mean those nodes will stand pat in a technology sense. Foundries, IP vendors and others will drive optimization into these nodes, which means opportunity for a long time to come.

Older nodes are being invigorated with new variations and options aimed at serving market opportunities for the Internet of Things, automotive and medical applications.

I see tipping points 1 and 2 as attached at the hip. Optimization is being wrung out across the spectrum of nodes as design teams march into the future and a cohesive EDA/IP ecosystem helps drive innovation, speed time to market and improve productivity.

This is the kind of bottleneck busting that Lanza means. As an industry, however, we just haven’t come up with a catchy name yet. (At Cadence, we call it “electronic system design enablement;” others have their own descriptions).

Lanza won EDAC’s Phil Kaufman Award this year for a lifetime of contributions to electronics design in general and EDA in particular. He has a deft way of describing the challenge ahead:

“If we don’t do this, innovation will slow down and our impact on society won’t be as meaningful,” he said.

That simple statement is actually quite profound. Given what we saw in 2014, expect some more societal transformation ahead.