Why clock domain crossing verification is a must for accurate signoff at the netlist stage for a first-pass silicon.
Clock domain crossing (CDC) verification has been an integral part of modern chip design flow for quite sometime. Traditionally CDC verification has been done during the RTL stage. However, for advanced designs and complex flows, there is significant logic optimization during RTL synthesis as well as backend flows at the netlist stage. This mandates clock domain crossing verification a must for accurate signoff at the netlist stage for a first-pass silicon.
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