Emulation Enabling Automotive Designs

Last week at CDNLive in Munich, the key topic at hand was automotive. It was pretty much a theme everywhere, and even had its specific personal track. My personal favorites were Davide Santo’s (NXP’s Architect) keynote on autonomous driving—very inspiring—and Robert Bosch’s overview of how they used emulation in a hybrid setup with ARM Fast Models for IP verification for automotive designs, making their emulation usage public.

As to setting up automotive challenges and trends, Davide Santo’s keynote was very insightful at several levels. One of the key graphs was about structuring automotive electronics along the vectors of “Sense”, “Think” and “Act” for the areas of connectivity (1), driver replacement (2), powertrain and vehicle dynamics (3), body and comfort (4), and driver experience (5). It clearly showed how Qualcomm complements NXP.

In his keynote, Davide Santo charted a roadmap of what he called the revolution of automated and autonomous driving, from “conditional” (SAE level 3) focused on 360^o sensing, behavior and safety; through “high automation” (SAE level 4) with a focus on redundancy, fail operation and recoverability; all the way to “full automation” (SAE level 5) with highest coverage, full redundancy and dependability.

What stuck with me the most was a realization that Davide pointed out: We don’t really want the car to learn what a human does, specifically because we humans do not have 360^o vision and lidar built-in (at least not yet). The car should learn its actions within the context of sensors and actuators it has been given.

As to emulation, it is well-known that Palladium has been used by CSR (now Qualcomm) for automotive, as well as NVIDIA and Renesas. While these are all semiconductor companies, Robert Bosch is a Tier 1 supplier—so more of a system company. Marc Lapassat (Verification Lead), Pascal Grippi, and Christophe Lafon talked about their experiences with Palladium Hybrid emulation in a presentation called IP and Driver Development in SOC alike Hybrid Environment. They also won the best presentation award for their track, which was well-deserved.

The context of their challenges was the creation and release for integration of several computer vision IP blocks that are embedded in a third-party SoC. The target technology is 16FFC, and the blocks are about 20 million gates with 3.6MB of memory. The ultimate objective was in-system IP validation, complementing RTL verification using real software drivers and ad-hoc validation test codes that were running on an ARM Cortex A-53 processor. They decided on a hybrid setup that is shown here:

The processor subsystem is represented as an ARM Fast Model and runs in a virtual platform based on transaction-level models on top of Cadence VSP (based on the Cadence Incisive Enterprise Simulator). The RTL of the IP blocks is kept accurately in emulation, at full accuracy. The interconnect is automatically generated using Cadence Stratus High-Level Synthesis (HLS), and the resulting hybrid configuration combines bit-accuracy and cycle-accuracy of the IP in their system environment with the capacity to develop, execute and debug large amount of software.

The team defined the key requirements to allow IP development in a cycle accurate SoC context:

• The availability of a software execution environment with good responsiveness
• Re-use of a known ARM software debugger (in Robert Bosch’s case, it was Lauterbach TRACE32)
• The availability of a debug environment with full visibility on the hardware when required
• Access to RTL registers in TRACE32 for software developers to view
• Availability of an environment like a product reference board
• Reduced size of the infrastructure emulation model to maximize the number of users on the emulator

To achieve these goals, the team used the following standard and customized capabilities:

• The Cadence DDR controller Design IP and DDR emulation model provided for the Cadence Palladium Accelerator/Emulator
• Standard connections to TRACE32 via ARM’s CADI interface
• The “Smart Memory” from the Palladium Hybrid
• A special RTL adapter to expose registers from the hardware to the software debugger

Bosch described how they are now using this setup with six users in parallel with two teams working in shifts. The main use models are:

• IP Validation with debug for software using Lauterbach and hardware for probes, signals, triggers and logs, with non-regression automated tests running overnight
• IP Debug supported with visibility into the RTL and schematics, as well as wave access for the complete design

Bottom line, the Robert Bosch team is now able to fully validate the IP blocks within the hybrid environment; they validated the software drivers and measured coverage.

At this point, they have reached a very quick and efficient turnaround time:  it now takes them less than 2 hours from RTL delivery to execution within the hybrid environment. Using high-level synthesis, the team can adapt to new interconnect design constraints for the interconnect during the project.

The automotive market remains a fascinating application domain, and is equally fascinating they ways technologies (like emulation) become indispensable to bridge hardware and software development and to enable automotive designs. The future looks bright, even though my days as driver in the car may be numbered…