Enabling Integration Success Using High-Speed SerDes IP

By Niall Sorensen and Malini Narayanammoorthi

Internet traffic volumes continue to grow at a breakneck pace, and the demands on SerDes speeds increase accordingly. High-speed SerDes play an integral part of the networking chain and these speed increases are required to support the bandwidth demands of artificial intelligence (AI), Internet of Things (IoT), virtual reality (VR) and many more applications in the works.

SerDes design is a complicated procedure, generally with a custom-built analog transistor-level design and a soft/hard custom register transfer level (RTL) for analog control, and in some cases a microcontroller to allow for flexible behavior and in-the-field updates. Due to this complexity, a multidisciplinary team of analog, digital, and physical designers and software engineers is required with support from silicon-validation and operations teams.

With the rapidly increasing demands on speed, time to market is imperative for ASIC companies when implementing SerDes in their designs. For this reason, it has become more time and cost effective to source SerDes from an IP vendor specializing in the technology. ASIC companies must be either very knowledgeable in high-speed SerDes integration or rely on their SerDes IP vendor to support them in their development. There are many areas of ASIC development outside of the custom analog/digital placement into ASIC design that require this knowledge, such as substrate design, PCB board design, supply noise, timing analysis and so on.

The role of the SerDes IP vendor is to ensure the effective integration of its IP into the ASIC following best practices. This article discusses how the vendor can help in integrating SerDes IP and through flow implementation, documentation, support and many other factors enable a successful ASIC design project and subsequent production ramp up.

Hookup issues
Some of the most costly issues that can occur in integration are pin hookup failures. The IP pin list is defined on the boundary of the IP, and it is the role of the ASIC integrator to connect the IP in a manner that ensures correct functionality of the ASIC. If a pin is connected incorrectly, it can often result in a costly silicon re-spin. Generally, correct documentation is enough to ensure the ASIC customer has the relevant knowledge to understand how to connect pins either to controller, registers or custom logic. Additionally, digital simulation should catch most pin hookup issues so long as the models are accurate.

However, there are various factors other than good pin descriptions and models that can be important. Many signals may be on a high-speed clock domain or require synchronization to an external clock domain for proper usage further down the chain. This clock domain information for each pin needs to be accurately documented as well as the clock/data/general purpose usage of each pin.  Rambus facilitates a thorough review early in the design cycle for the customer with our design teams to ensure correct pin hookup on the external boundary of the IP. The IP design team reviews the physical hookup on the ASIC side to ensure the correct pin usage is fully understood.  A list of synchronizer cells used externally to the IP provided by the ASIC integrator enables the IP design team to ensure that clock domain crossings are properly handled.

Simulation of the design
When an IP is delivered, simulation models are typically one of first views of interest.  This allows checking interoperability of the IP with the controller and other blocks in the design.  The IP should be simulated as a standalone design and reviewing this helps the integrator understand how to hook up the design in the system simulation environment.  Further documentation is provided to ensure correct usage of switches and flags in the simulation environment.  As a next step, the IP along with the other components should be simulated for the various modes of interest including functional modes, scan modes, and loopback modes.  The test plan should include all possible modes of usage of the IP including test and debug modes. It is best if the bring-up lab engineer has access and familiarity with the testbench and models as this will help speed the bring up process in case a debug situation arises.  It is also good practice to run a gate-level simulation once the IP has been routed to rule out timing related violations. Rambus enables customers with a simulation review to ensure proper coverage of the functional and test modes prior to tape out.

Timing analysis/place and route
SerDes clock speeds in the digital layer are increasing to rates of 1Ghz and beyond. As data rates increase and bus widths remain steady, this is a natural progression, e.g. PCIe Gen4 running at 16Ghz with a 16-bit bus width and a 1Ghz clock speed. Higher speed clocks result in lower design latencies on the data path which is beneficial for communication speed over networks. However, this creates a challenge for timing closure with a SerDes design that can include a complex array of clock loopbacks and control blocks running at these transmit (TX) and receive (RX) clock speeds. If the digital layer of the SerDes design is provided to ASIC integrator in a soft Verilog or VHDL format, the ASIC integrator is expected to synthesize, place and route (P&R) and close timing successfully on the design. Given that the ASIC integrator is generally not intimately familiar with the IP design, this can present a challenge.

In order to successfully close timing, Rambus provides the ASIC integrator with synthesis design constraints (SDC). SDC provides a high-level description of the clocking scheme for the design including clock definitions, clock groups, clock frequencies, clock crossing domains, non-standard clocking schemes, etc. In addition, an application note is provided including detailed information on clock mux design, suggested clock tree timing budgets for the critical high-speed TX and RX data path, and instructions on clock balancing for loopback and mission mode clocking.

For the analog portion of the design, Rambus provides liberty timing models for the analog front end (AFE) portion of the design that is a hardened custom transistor design. The liberty timing model specifies the timing delays on the interface between the AFE and the digital layer. Rambus also supports annotated gate-level simulations to catch any functional timing issues that may not be caught using static timing analysis (STA) tools.

Board/PCB design issues
As data rates increase, board design becomes increasingly challenging. Many factors must be accounted for when designing a PCB board and package including:

• Crosstalk
• Impedance matching
• Intra-channel skew
• Supply decoupling
• Insertion/return loss
• Regulator supply noise
• Connector choice

Rambus provides a detailed application note with instructions and specifications for the ASIC integrator to have signoff criteria for all the aspects of channel and noise quality outlined above. Although many ASIC integrators are very knowledgeable of high-speed board and package design, and while outside the design of the SerDes IP, it is always helpful to provide clear instructions to avoid these kinds of issues. In addition, Rambus provides several debug tools as part of the IP to analyze signal integrity (SI) and channel related issues, including an eye diagram and an impulse response analyzer to find channel reflections, crosstalk, etc. See the figures below.

Figure 1: Example Eye Diagram

Figure 2: Example Impulse Response Diagram

Bring-up readiness
There is a lot of excitement and nervousness for the design teams when a chip finally comes back to the ASIC integrator’s lab. There is a lull in integration activity of several months between tape out and the chip’s return. These months can be used productively to ready for the chip’s arrival.  Rambus’ application engineering team suggests the following questions be asked. Do you have all the equipment you need to bring up the design? Have you done a full package and board review to remove SI surprises? Have you run system simulations?  Have you informed your IP providers of when the chip is expected so they can plan on support? What are the logistics of having your IP provider application team travel, if needed? Have you had the relevant portion of your test plan reviewed by the IP applications team? Have you familiarized yourself with, and simulated, the different test and debug modes available? If updates are needed, what is the procedure to obtain and implement them?  You can never be too prepared, and with planned reviews with your IP vendor support team you can minimize bring-up issues with new chips.

Silicon compliance, debug and failure analysis
Compliance, debug, production yield, and system debug pose interesting challenges during customer production ramp up.  Often system issues are brought to SerDes IP vendors since these eventually result in poor link performance. The IP needs to have sufficient isolation test paths to isolate the issue at hand. While isolation sounds basic, the problem gets compounded by repeatability challenges, board-to-board variations, socketed vs. soldered assembly, etc. Once isolation of the system failure is identified, the issue must be reproduced to understand trigger points. This then leads to cause-and-effect analysis. It’s often not systematic issues but one-off Monte-Carlo variant issues which tend to be tricky but important to root cause. The IP should have enough observability to enable such debugs which is often challenging when working at the high speeds of today’s designs. Further, the IP vendor should ensure the design can meet the compliance targets through sufficient design verification of the IP or through design configurability. This phase can often be demanding and high pressure, and the Rambus team helps make it as seamless as possible.

Conclusion
With the relentless demand for more network bandwidth, the speed of SerDes will continue to climb. Increasingly, ASIC companies will turn to 3rd-party SerDes IP providers for these critical building blocks motivated by considerations of time-to-market, lowering total cost, and reducing risk. Choice of IP vendor needs to encompass the vendor’s ability to support all the elements of IP integration including simulation, analysis, package and board design, bring up and system debug. Though greater complexity is introduced with every speed bump, the application of best practices with the right IP choice will ensure successful implementation of new ASIC designs.

—Malini Narayanammoorthi is a senior manager of applications engineering at Rambus.

Additional Resources:
SerDes Signal Integrity Challenges at 28Gbps and Beyond
Going Beyond GPUs with GDDR6
Rambus 112G XSR and LR SerDes PHYs