NeuASIC platform Includes AI accelerators for 2.5D/3D ICs.
ASIC provider eSilicon focuses on high-performance devices for communications infrastructure, networking, and other data-center applications. Using 7nm TSMC pro- cess technology, it has developed ASIC-design platforms under the NeuASIC brand. Each platform includes hard and soft macros for networking applications along with a new architecture and intellectual-property (IP) library for building AI accelerators.
The NeuASIC platforms give designers a variety of power-optimized memory compilers, serdes, and 2.5D-IC interposers. The 7nm library includes a 56Gbps serdes, High Bandwidth Memory 2 (HBM2) PHY, and ternary- content-addressable-memory (TCAM) compiler, as well as networking-optimized I/Os and other components. The eSilicon design team is also working on a 112Gbps serdes, which it plans to tape out in 1Q19 on a 7nm test chip.
To maximize memory bandwidth, the company manu- factures networking products in 2.5D packages using silicon interposers to combine the ASIC die with stacked DRAM chips, as Figure 1 shows. For AI accelerators, NeuASIC will enable designers to integrate a custom deep-learning accel- erator (DLA) in an ASIC chassis comprising a CPU, scratch- pad RAM, and HBM2 interfaces.
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