Experts At The Table: 3D Stacking

Second of three parts: The upside and downside of standards; build, buy or re-use; the effect of more layers on yield, and what still needs to be done.

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By Ed Sperling
Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice president of marketing at Atrenta. What follows are excerpts of that roundtable discussion.

SMD: How important will standards be in 3D?
Radojcic: We definitely need standards. But before the world invents standards we have to have a pretty good image of what we’re doing. With Wide I/O memory that was easy. JEDEC was developing the standard so it was all good. If you open the door for logic on logic, it’s not going to be seamless. You really need to think about what kind of partitioning makes sense. You’re not going to want to split your clocks. We first need to do that as an industrial community.
Wingard: In the logic-on-logic space it’s going to be a closed shop model first. It’s going to be the same people designing the chip above and below.
Subramaniam: Yes, they will have control of the area and the design. The other place I see logic working is in re-use. A company could build the building blocks and then use those building blocks for different applications. Again, that will be a closed-shop approach.
Wingard: Then you need standards. Everytime you mention re-use you will need a standard.
Subramaniam: At least you will need an internal standard.
Wingard: One thing that’s different about the way we’ve done packaging before is that we had a layer of the package in between that had the same protocols and signaling levels even though our bond patterns didn’t match exactly. We relied on PCBs to make things match. With TSVs we don’t have that anymore. You have to agree on everything, from pad pitch to signaling all the way up that stack.
Radojcic: And it’s all interdependent. Figuring it out is a big problem.
Wingard: That’s what makes interposers so interesting. They’re the bridge for things like logic on logic. I think 2.5D logic on logic will happen well before 3D logic on logic for exactly these reasons.
Radojcic: For companies that can tolerate the form factor.
Wingard: Yes.

SMD: Isn’t one of the big issues focused on responsibility? You may have two perfectly good chips, but when they’re put together they don’t work properly.
Radojcic: There are things before that we need to figure out. We need information from the memory guys for stacking memory on logic so you can manage your hotspots and mechanical interaction. We need to agree how we exchange information between us and what that information includes. Then, when it comes to the building side, we need to create a supply chain business model for who owns what.
Hogan: This isn’t trivial. It’s a lot of work and we will solve it. But why bother? Let’s back out for a moment. The SoC is the way everyone delivers system value today. That’s dominated by the ARM processor. Everyone uses something that looks like an interconnect. On that interconnect people differentiate themselves with two things. One is a peripheral device. Texas Instruments is a great example of that. Someone else might add memories. The second thing is software. What 3D allows you to do is consider other things and other arrangements. We can spend a lot of time talking about the margins on SoCs, but they’re 50% or 60%. That’s why everyone does SoCs instead of discretes. There’s more value in the system. There will be a lot more integration of peripheral devices and software. That’s what’s exciting about this. It’s not to trivialize all the EDA work and the supply chain, because there’s a lot of work, but that’s what’s really interesting for me. This will allow more democratization of a design.
Gianfagna: You were talking about how the ecosystem would evolve. First it would be monolithic and internal by one company. Then you try to figure out how you do re-use, and then there will be third parties. That’s exactly how the existing 2D ecosystem evolved. That’s depressing. It says we didn’t really learn anything from 2D. You don’t think we’re any smarter?
Wingard: We’re starting with the standard interface stuff. Logic on memory is the early example. It’s not a closed shop today.
Subramaniam: It is a closed shop. Samsung owns the processor and the memory. They already do this Wide I/O design. They’re not going to wait for the standard. There will be a standard eventually, but they’re going to drive it.
Wingard: My guess is that’s not the volume driver. It’s a technology-proving vehicle. But independently, it will be standard interface first, then logic-on-logic in a closed environment, then we’ll figure out what else we can standardize on. To think that we’re going to get standardization ahead of where people know how to use it is very scary.
Gianfagna: So we’re stuck with standards driving the ecosystem and not the other way around?
Hogan: Anytime you have standards in place you lower the barrier to entry. That accelerates the ability of the ecosystem to grow. But there will be companies like Samsung that can’t wait, so they’re going to do their own version. And they have enough volume to do it. For the rest of the world they’ll have to wait for this chip-to-chip and logic-to-logic capability. But it will happen.
Subramaniam: On the logic-to-logic, I’m still not convinced a standard will evolve. The reason why a Wide I/O standard evolved was that you need a third party. Nobody is going to be designing their own memory. A third party is necessary. But with logic on logic, people may view it as a competitive advantage not to have a standard. There’s no reason, if I develop my own logic-on-logic, that it should hook up with a third-party logic design. I’m not agreeing with logic on logic becoming a standard.
Gianfagna: At one level that’s true. People don’t want to be homogenized.
Hogan: At CES Microsoft said it was going to use an ARM-based SoC with an Nvidia block. An Nvidia block? If you think about Xbox development they started out doing everything themselves, then they gave up and went to ARM. They’re not even doing their own graphics processor anymore.
Wingard: PoP (package-on-package) has been about memory on logic. One common version is baseband on application processor. Right now that business is done partly because some of the companies don’t have their own baseband assets. I would expect that to be logic-on-logic in the future. The more advanced basebands need more access to memory than they did before. There’s going to have to be some reasonable baseband connectivity in the future. Even if there aren’t any industry standards, with logic on logic if you want to get any re-use you’re at least going to need company standards.
Gianfagna: You guys are debating whether you integrate IP blocks on one die or two. You’re going to start with a certain number of building blocks. But if you have one at 22nm and one at 65nm, how do you connect them?
Wingard: I don’t think the model for a long time will be, ‘I’ve got this system to go build and I’m going to partition it across a set of dies the way I partition it across a set of FPGAs.
Gianfagna: Why?
Wingard: Because of legacy and because it’s too expensive. With legacy I’ve got something that’s been proven. But I’ve got something else I want to change, so this other die is the one with the new stuff on it. It’s that kind of re-use and how systems evolve and not having the assets because this thing comes from somebody else. All the logic doesn’t have to end up on one die.
Radojcic: There are many new constraints, both physical and architectural. The idea is that you take one die and slap it together with another die. But when you start thinking about it more and more it makes your head hurts. There are all these degrees of freedom that are interdependent.
Hogan: If I’m Cisco, I’ve got 35 million lines of legacy code I have to run in my router. How do I upgrade? It would be great to have an interposer because I can leave all that old code. Routers, servers and base stations are going to be loving this. The mil/aero guys are going to love this, too.
Subramaniam: If you have a 28nm chip, your upgrade could be done with an older chip geometry, and then you can use an interposer to slap the two together. Your equipment and design costs are going to be much lower with this approach.

SMD: There are two trends here. One is to build more and more on the SoC. The other is to set up all these separate processors. Does 3D move it all into one device and does it become more of a logical partitioning problem?
Gianfagna: Yes, but it’s going to happen slowly. You’ve taken what used to be on a printed circuit board and integrated it into a device. The more planes you add, the opportunities to mess up go up exponentially around thermal, stress, mechanical, heat dissipation, TSVs that don’t have anything to do with an interconnect. You can think about integrating multiple pieces of the system in the same package, but it’s going to take a while to get there.
Hogan: If you’re talking about integrating silicon, try getting TSMC to add two more mask layers or two more stops as the wafer travels around the fab. You need an enormous amount of volume because they like to minimize risk. Otherwise you’d need your own fab.
Subramaniam: If you put a TSV on a chip you’re effectively creating three or four layers on top of your 10 layers of metal. That’s going to happen sooner or later. The question is how many more layers will you get. There will be a limit.
Hogan: When we did studies on SiP (system in package), the yield is a linear function with the number of layers. Every time you add another layer it’s worse yield.
Subramaniam: But these layers are very coarse.
Hogan: I understand, but what should your yield be? How do you even test these things. The system is only functional when you have both die together.
Subramaniam: And you cannot use wirebond.
Gianfagna
: You might also get a really fancy boundary scan and isolation logic.
Radojcic: We’re having a discussion the 3D industry already went through. The first discussion was, ‘This is really cool.’ The next discussion was, ‘How am I going to do this? How am I going to test this?’ The classic hype curve has been followed. There is a trough of disillusionment. But some of these things are already solved or solvable. It’s good to focus on, ‘We can do this. We can do memory on logic. So let’s focus on the work to be done.’ The work that’s left to be done is design exchange formats so you can model thermal or stress behavior from die A to die B, and you need feed power from tier two to tier one. We just need to get our act together and create standards.
Hogan: If you have standards in place you can get things done. If you have to integrate this stuff, no one lets the standards out and you have to fight for them—or you get competing standards.