Experts At The Table: 3D Stacking

Last of three parts: Standards, killer apps, thermal issues, who wins with 3D and whether all the problems can be solved.

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By Ed Sperling
Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice president of marketing at Atrenta. What follows are excerpts of that roundtable discussion.

SMD: So have we learned anything over the years from standards?
Radojcic: I do think we’re smarter than we were. It’s easier for tools guys to look at standards and subscribe to them than in the past. There isn’t as much ‘Mine is better than yours.’
Gianfagna: There’s a lot of work to create the standards. There’s a lot of work on the EDA side and there’s a lot of work on the process side. And then we talk about all that work being front-loaded. But the uptake is really slow. With 3D we talk about memory and processors and then go to something else. There’s a tremendous investment that has to be made over the next 18 months, and then we may not get it back for seven years.
Hogan: Xilinx has been shipping its prototype in limited production. What it always takes to get everything going is the killer app. Who would have thought about a full-finger touch-screen for your phone until Apple showed us we needed it. Now everyone has it and Apple is fighting with Samsung for displays. So what’s the killer app? I was not interested in touch displays. They have low margins and it’s a bad business. But suddenly touch displays are hot. What will it take for 3D to kick off?
Subramaniam: You don’t have to have a killer app. In the Xilinx case it’s pure economics. What they have done is create a tile structure for the FPGA. Rather than have a big FPGA die they have taken slices and hooked them together. The yield is inversely proportional to the area of the chip. If they went to a traditional FPGA model their yield would be extremely low. By going to a tile model they will have many more good tiles and their overall cost will be significantly better. Where you are talking about arrays or repeatable structures there will be benefits. In multicore designs, why build a 16-core chip? You can build four-core chips and put them together.
Hogan: I don’t disagree with that. But I do say it’s the system appetite that drives all of this stuff.
Wingard: That’s what makes Wide I/O so interesting. There is a system appetite in smart phones right now for a massive increase in acceptable bandwidth that we don’t know how to get to without doing this. That’s why so many people are aligning around Wide I/O.
Radojcic: Yes, and even though we doubted that phones would do this, we hurt in one area even more. Look at all the things you’re putting in a phone. It has to have a small footprint, so many gigabits per second of bandwidth and low power. It’s painful and 3D can help. Phones will probably be the killer app and most people are now saying it will happen in 2013.
Hogan: Video, too.
Wingard: Yes, video content with minimal power.
White: For mobile applications, does 2.5D suffice or do you really need to go to full 3D?
Radojcic: We are pursuing full 3D and so are most of the people in the phone business, primarily because of the form factor and cost. If you think about an interposer, you’re adding another die to the cost. Conceptually an interposer is an elegant solution and it works fine for someone who sells a product for $100. If you throw in a $1 interposer it’s no big deal. But if you’re making a $5 die and you throw in an interposer, it is a big deal

SMD: How about the thermal issues in 3D? Are they worse?
Radojcic: Thermal is an issue in 2D or 3D. It’s always an issue. 3D gives you some opportunities to help with the thermal. You can drive the power down. It can work as a heat spreader. It’s harder, but you can engineer it correctly. Do we have the infrastructure for dealing with thermal? Some of it. You can do thermal analysis. But can you take thermal information from a memory producer? No. You need to do a custom job to interface with the memory guy to see where he anticipates thermal issues. What we need are exchange formats. The tools are there. We need a methodology.
Gianfagna: There’s an analogy with timing-driven design. It used to be that you’d do timing analysis on the outer loop, then you’d do place and route and it would become part of the inner loop when you couldn’t get timing closure. The same thing is happening here. There are standalone tools that will do thermal analysis at the outer loop. That’s not going to work for a long period of time. You’ll need them in the inner loop as part of your iterative placement and partitioning. That’s not an unsolvable problem, but it is another hurdle across.
Wingard: And in a phone it’s mode-specific. The thermal patterns for an SoC are different, depending upon the use case. If someone uses their phone to watch a video it’s different than using it for a phone call.
Radojcic: And it’s different if you’re doing it in a hot car in Arizona.
Wingard: Some of this happens as a result of PoP. What used to be a package now becomes a heat source. With TSVs the granularity is finer, but if you’re looking at the hot spots on a chip that someone else gave you it’s going to be really difficult to work with.
White: You have to work with a transistor-by-transistor power model, and you use that to drive your decision-making.
Wingard: But it’s so use-case dependent.
Subramaniam: It’s not that bad. You’re not talking about different materials. It’s all silicon, so it’s easier to model. You can do the modeling and the analysis.
Wingard: And it’s more important to model.
Hogan: It will follow the arc. There will be details of transistors, then someone builds the lump model, and the lump model won’t give you enough degrees of freedom so someone will build a better model with more granularity—but not too detailed because you don’t want to slow it down in simulation.
Gianfagna: If you want to do this analysis, is it enough to do it structurally or even from a vector input point of view? You need to start running software scenarios. Bringing software into a hardware architectural design is interesting today, but it will be critical in the future.
Radojcic: This is all true and scary, but thermal is a good conductor. So do I need granularity for every transistor? Probably not. One transistor may not be quite as hot as its neighbor, but it will be pretty close. And do I need to run all these different use cases? Probably not all of them. You can say you’re going to burn most of your power here. Everything needs to be use-case and software-specific, but a lot of it we can do now. We can do thermal that’s plus or minus ‘x’ percent.

SMD: Does 3D change who makes money and where they make money?
Gianfagna: One of the Holy Grails for EDA is whether they can be a cost-enabler instead of a cost of doing business. And can they partner with customers to open new markets? Beyond that, who’s the general contractor? You’ve got a 3D stack that consists of multiple die that are known good quantities with a silicon interposer put together for an end customer. There are yield risks, assembly risks, inventory risks and design risks.
White: The foundry is also going to work very hard to get a cut of that.
Subramaniam: For us it’s just another piece of silicon and another way of packaging silicon. We don’t see it as any different from what we’re doing today.
Gianfagna: The supply chain is more complex.
Subramaniam: That’s true. And there are some issues with test. But by and large it’s very traditional.
Radojcic: It is different. Today you don’t go and buy memory and own the memory inventory.
Subramaniam: There are some differences, but they’re all manageable. We do multi-chip modules and PoP. We do all the different packaging technologies that are out there. This isn’t just a packaging solution, but it’s not all that different.
Hogan: Embedded in that is a question of where the value flows. The SoC guys still get the majority of the value. The question is who picks up value down below? Is it EDA or the enabler or the functional equivalent.
Gianfagna: The system guy gets most of it because that’s who defines the software and the delivery vehicle.
Hogan: So the rich get richer.
White: I don’t like that answer but it is the answer.
Hogan: Joe Costello described EDA as five dogs and one dog bowl. Below the system that’s what it’s going to be like. The value will flow differently, though. EDA will get some. I don’t think the foundries will get it all. [Value-chain producers] will get more.