Experts At The Table: Designing At 28nm And Beyond

Second of three parts: Changes in the supply chain; what happens to little companies; rethinking business models; disruptions caused by stacked die.

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By Ed Sperling
System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz, Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), and Charlie Cheng, CEO of Kilopass.

SLD: Where will biggest challenges be at future nodes?
Schirrmeister: For us it’s the combination of hardware and software that gets interesting. You may have a network operator determines he wants coverage for the NFL on Sundays. That trickles through the design chain of what the network needs in terms of bandwidth and what the devices need to be able to process. As an EDA vendor, there are huge challenges for us because what used to be a small IP model has grown into a subsystem. People are building chips as an assembly of subsystems. The integration and the verification become a big issue at both the subsystem and the system level. There are lots of ways to grow.
Janac: I see things getting fragmented, concentrated and disintermediated. Nobody can afford to do everything themselves, so you wind up focusing on your core competencies. The people in those core competencies become more concentrated. The chip world also gets more concentrated because there won’t be many people who can afford to build a platform at 20nm. But the components for that platform are going to be disaggregated. Companies will have to outsource a big chunk of those designs and a lot of the tools they used to do themselves. So the little chip companies die. They will have a really tough time, particularly at the leading edge. The EDA industry has a lot of problems because it will be sharing the volume, which is going to explode, and it will be hurt by the fact that the number of projects will decline. You wind up with someone owning 80% of the processor market, someone owning 80% of the interconnects, and someone owning 80% of the memory. The DSPs get concentrated. Tools get concentrated, where someone owns place and route and someone owns simulation and ESL.

SLD: But you have to redefine what’s a chip company, don’t you? Are Open-Silicon and eSilicon chip companies?
Janac: Yes. And if I’m a small company I have to go to Open-Silicon or eSilicon because I can’t afford a staff of engineers to get a chip out.

SLD: But traditionally they were not considered chip companies.
Zahiri: They’re an aggregator of chip demand. Maybe eSilicon and Open-Silicon become the equivalent of midsize to large chip companies, aggregating the demand of the little companies that have to go to that model to be competitive and survive in the marketplace.
Sherwani: Along these lines, one of the challenges I see is that we’ve set up the market to expect 50% gross margins and 30% net margins. If your IP is coming from ARM and Kilopass and other companies, then how do you achieve those kinds of margins? You can’t. And if you can’t achieve those kinds of margins then you also have a business problem, and your business structure has to change. If you do everything in-house you’re not paying all the up-front fees to IP vendors. So first there is a problem of size. And second, even if you have the size there is a profitability problem with respect to the expectation that has been fed to Wall Street.
Janac: If your gross margin goes down, your operating margin has to improve, which means you can’t do enough R&D. So instead of using 25% of revenue for R&D you can only afford to do 10%. The PC guys are reasonably profitable at 25% margins because they don’t do any R&D. Intel does it. That’s why people are starting to outsource the IP. They can’t afford to do the R&D as the gross margin drops.
Sherwani: That’s one piece. But if you look at what’s going on in chip companies, the R&D budget goes down for IP, but it doesn’t go away. It goes into software. The number of software engineers is increasing. The market expectation still remains for hardware gross margins, but your expenses are going up.
Schirrmeister: You can’t just look at the chip in isolation. You have to look at it holistically. One large OEM says it’s losing money on every TV it sells. They have to get it back other ways. You can’t look at these things in isolation.
Janac: It gets back to the business model. If you don’t have a good business model and you just keep squeezing the margins then you’ll go out of business. But there are people who have innovative business models, like Amazon and Apple, that can afford to sell the hardware at cost.
Cheng: Worrying about margins and R&D is like worrying about the 120 companies that went out of business selling cars. As businesses mature, the technology content gets very high and it costs a lot. It’s not that companies don’t have good gross margins. There are a lot of companies with margins of 60% or more. But the ones that assemble IP and add 10% original content are not going to be very successful if they don’t differentiate, and they won’t be good customers long-term for the EDA vendors because 70% of those chips are memory and another 20% are IP that’s licensed from the outside. So they may only be doing 10% of the chip. This is why EDA revenue has been flat. If you look at the surviving car companies, they’ve been very profitable over time because there’s a high barrier to entry and it’s a fixed market.

SLD: But more pieces have to go together into something that’s coherent, and that’s more difficult than ever before, right?
Janac: I just met with a customer that spent $500 million on their platform and they have 180 IPs. They still make most of those IPs themselves, but integration is the issue.
Cheng: Integration isn’t any worse today than in the past.
Janac: It’s absolutely worse. And the reason is that you have an incredible amount of computing in smartphones, and that’s even trivial compared to what it’s going to be. You can’t afford to keep that device turned on except at times when you need it. One of the complexities of 20nm and 14nm is that you need a portion of the chip to do its job and then you shut it down. From a power perspective, you can’t afford to keep it on. And you don’t want it to be big, so you can’t afford a huge battery. It is very complex. You have frequency domains, power domains, power regions. You have as many as seven modems—WiFi, Bluetooth, CDMA, GSM and LTE.
Schirrmeister: What customers are telling us is that getting to an acceptable confidence level in verification is a very difficult thing, driven by the integration of all the components they have. Given that you’re taping out a chip and you can’t make a change tomorrow—that’s the pivotal point where you have to have enough confidence. The integration challenges are huge.

SLD: The promise of stacked die is that if you have a base platform you can start shifting into vertical markets quickly because a lot of the integration is already done, right?
Janac: Yes. The application processors that are being made for phones can be shifted into dashboard control, automotive infotainment and home gateways. What’s also going to happen is that the low end of the SoC market is going to disappear because the costs are too high. You’ll get 3D silicon, where people are selling dies with specific functionality on trailing-edge processes. You’ll wind up with FPGA SoCs.
Sherwani: But that’s a good thing. You could build viable chip companies that are on trailing processes with known good die that we can put into 3D stacks. You don’t have to push them all the way to 22nm. There’s no need for that. A lot of people will stay on 65nm, and that will justify keeping those fabs alive for a long time. It actually helps with the overall investment we need to put into 14nm.

SLD: Are the specialty fabs that are coming online capable of doing all this integration work?
Sherwani: They don’t need to. The interposer technology we have today doesn’t have to be much better. At 22nm you’ll see many people bringing 3D chips buying known good die from a bunch of people and putting these MCM-style 3D chips together. That will lead to many companies, which we consider sub-optimal today, becoming viable. And I don’t think these small SoC companies will disappear. They will start doing specialty silicon.
Janac: They will be the known-good-die companies.
Sherwani: Yes. They will be working with GlobalFoundries and TSMC at 65nm. They don’t have to run at 1.2GHz. They can run at 300MHz and be just fine. And you don’t have this area constraint. So area constraints and power constraints can be reduced. Today you have one chip and something that is 1.2GHz can run fine at 100MHz. Not everything is being pushed to that level.
Janac: And then you’re moving from 2D integration to 3D integration. That opens up a whole bunch of opportunities that are untapped today.
Sherwani: Just because of 3D, there are huge opportunities. I also think that IC design and computing will completely change if we can change the memory. The idea in the past was to dumb down the memory because you could pull the gross margin into the microprocessor. After 25 years of dumbing down the memory we do have standard interfaces, but memory isn’t doing much. When you look at 3D memory, it has 20X the performance of DDR3. It is one-sixth the power and one-tenth the space of DDR memory. A new era of intelligent memory will do a lot more than just keeping the bits. It will become very close to the processor, which changes the processor design. And many new applications are possible. If the architecture changes and memory and processors are very close together, many new things can happen. That is what you will see in the next five to seven years. You will be able to put terabit memories on top of processors in the same 3D package.