Experts At The Table: Multi-Foundry Strategies

By Ed Sperling
Semiconductor Manufacturing and Design sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; John Murphy, director of strategic alliances marketing at Cadence; Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics; Bob Smith, vice president of marketing and business development at Magma, and Linh Hong, vice president of marketing at Kilopass. What follows are excerpts of that conversation.

SMD: As we move to the next process node is multisourcing realistic? Everyone will have different processes and approaches and tools.
Murphy: Market segmentation is an important consideration here. If you look at the fab lite trend, it’s reaching the point where the early majority is adopting it. These are large companies that have owned fabs. There are about 15 of these companies.

SMD: You’re talking about companies such as Freescale and TI?
Murphy: Yes. Some are clinging to the old style of controlling everything even though they don’t actually own it. They want to control the libraries and the IP. That creates an infrastructure problem for them as well as increasing risk. If they’re trying to differentiate themselves around that, it makes sense to them. Other companies are saying that if they can’t differentiate themselves in hardware then they’re going to differentiate in software. There are a few nexus points. One is at the system level, where you make hardware-software tradeoffs. Another is at the IP level, where you select and maybe re-characterize IP quickly through some kind of engine blessed by the foundries. And then there are the hardcore semiconductor guys who want to control the process. If you take all three of these you get a representation of what’s coming at the very advanced nodes. Those are going to be hard and expensive to get to. The companies going to 20nm are mostly the processor guys, and they’re trying to control the process. The next guys will care about schedule, cost and risk. Schedule matters to everyone.
Buehler-Garcia: They also care about access to supply.
Murphy: That’s true. It’s access to supply, power, performance and area, and process because it’s all about compute performance. The next wave will be about schedule and risk, which is where you start considering multiple foundries. The early guys are going to partner with foundries because it’s so hard to get there. As that stabilizes, you’ll see a change.
Ng: I don’t agree. The lead guys have the largest volumes. They expect a very fast ramp in a very fixed market window. The discussions we’re having at 20nm involve a multisource strategy because they know their volumes are high and they do not want to be held hostage by any one manufacturer that may lock them in.
Buehler-Garcia: Is it really being held hostage? Or are they looking at this and saying, ‘Let’s be rational. If hit my number I will have 2.5 fabs of wafers. I’ve got to be able to break this out to multiple foundries so the risk to both of us is reasonable.’
Murphy: On that second wave, the processor guys look at a second source for precisely that reason.
Ng: It’s a supply assurance issue initially, but the later this goes on the more it becomes a cost issue. You’re trying to get a lower cost. If that’s the issue, then having to do a rip-and-replace doesn’t make any sense. That’s cost-prohibitive. That’s where you should look at where you can take the GDS II.
Hong: The reality is the world is getting smaller. There is so much consolidation going on that the big are going to get bigger and their volumes are going to get bigger. Being captive to a single foundry will not make sense for them. What worries me, though, are the mid-tier companies. Those with a couple hundred million dollars in revenue need a strategy to be competitive, and that’s also multi-foundry because it frees them from being captive to the pricing of a single foundry. They cannot develop all of the ecosystem and the IP themselves. There are quite of few tools out there that will do translation from one database to another to streamline the flow for a multifoundry strategy.
Buehler-Garcia: Those tools will get you started, but they won’t finish the job.
Ng: The midsize companies are caught in a vice grip because they don’t have the engineering resources to do the same design twice, but they also don’t have the business ROI to drive their process among different manufacturers. Many times they don’t even have the mindshare with EDA and IP companies to help them.
Buehler-Garcia: It depends on how your $300 million comes up. We have some customers that do 4.5 million to 5 million die per week with only two products, so that $300 million is for two products. That’s a big load on a foundry, especially if things tighten up. That’s an opportunity for the ecosystem to help them. But there’s another reason to help them, too. The lead guys hit the node hard, then after Christmas they drop it and move onto the next node. So you have $6 billion in fab infrastructure sitting idle. That’s not good for anyone. If we can help get the next wave in sooner, that’s good for all of us.
Smith: Looking past 20nm, my guess is we won’t have many companies. The big will get bigger, but what does that mean to the rest of the industry?
Ng: I think that is a challenge for the whole industry. That’s why you see most customers at the leading edge looking at 28nm or 20nm, but there are only a few designs that are even available for consideration. Even foundries are dropping off like flies because the next investment will be tens of billions of dollars. There will be fewer customers. They will continue, however, to drive the next process development. Those guys are getting larger, but the number of foundry players and the number of ecosystem players who will support these nodes will drop off. It’s an ROI game.
Smith: I can envision the industry going the other direction, too, so we’re all an integrated company again.
Ng: In the foundry business we’re always thinking about ROI. Even foundries and others in the supply chain will be forced to look at new business models on the cost side of it. The Common Platform alliance is a cost-sharing, best-of-mind development. Our cost of the next leading-edge node is one-seventh. That’s a strategic advantage. Other folks in the ecosystem will have to look at how you still deliver best-in-class solutions in a way that is economical and still allows you to be there.

SMD: What happens when we shift to 2.5D and 3D stacking? Does that change the dynamics of all of this?
Buehler-Garcia: It changes the flow. The supply chain is dropping off because of the cost of doing 20nm. The cost of building and supporting the number of decks and checks is a ton of people. But then the question comes back: ‘Does that mean that no one comes behind?’ Are there only three or four companies that go down to 20nm and all the IP with it? Or is it really about the gap between the first wave and the second wave, and we’re concerned that the second wave may not show up on time? They will show up eventually. We heard the industry was going to die at 90nm because of mask costs. We figure out a way to do it. But what has changed is the dynamic of when you hit the node because of ROI considerations. That’s where 2.5D and 3D come in. You can go up and still stay at the node you’re on.

SMD: Or you can buy a 20nm piece of logic and slap it onto 180nm analog, right?
Murphy: There are a number of challenges with 3D. It’s a technology enabler for a business model change, but if a piece of technology fails and it’s two tiers under a stack, how do you go get that? Or how do you make sure things will work before you put it together?

SMD: But it’s also harder with real 3D stacking than with 2.5D system-in-package, right?
Murphy: That’s true. The risk is still there with 2.5D, but with 3D it gets even more so. That’s an enabler for people to change how they integrate, and how IP is exchanged for value in the industry. Whether it’s delivered as a chip or soft IP or hardened IP, it gets integrated into a big SoC or stacked onto a 3D IC and allows semiconductor companies to have more flexibility in their business model. If you look at the risk in a 3D IC, but if it failed on your whole SoC it’s the same kind of risk. It’s just that the technology is new.
Buehler-Garcia: But 3D is another factor of multisourcing. If you really want to get a piece of flash memory, you buy it from the memory vendor. Why should I pay GlobalFoundries or TSMC for that bulk CMOS? But now you also have two sources of supply that you have to manage. It’s another factor you have to consider.
Murphy: It makes it more interesting. How big of a die can you yield at 90% versus how can you yield a module reliably with the right physical characteristics so it doesn’t overheat?
Buehler-Garcia: If you look at what Xilinx did with their 3D stack, at 28nm that would have been a 24 x 20 die size. If you just run the math on defect density, that’s a problem. If you split that into four tiles, at least you have a shot of getting it right. It’s not a long-term solution, but it is a strategy to get into the node and yield quicker. That’s an interesting tradeoff.
Ng: That’s exactly what it is. It’s trading off the current limitations of designing a 3D IC with the verification and packaging challenges vs. getting to acceptable defect density on larger die. The infrastructure for 3D is not mature, and standardization efforts are still ongoing. It’s a different way of looking at it. We don’t look at 3D as a way of dealing with legacy technology. The inquiries we get are at the leading edge. It’s an area we’re doing development in, but it has it’s own challenges.
Hong: Those challenges will have to be overcome. With the shift from high k/metal gate technology to FinFET to a new germanium or gallium arsenide substrate, that’s all happening too fast. There’s a lot of risk in all of those changes, along with new tooling and PDKs. That’s what makes 2.5D and 3D so promising. Your I/O’s don’t have to be in 20nm. And with DRAM and embedded flash, you can just have that on another die.
Buehler-Garcia: If it’s a non-standard process, then taking it off [the die] makes sense. If you get to 28nm you have plenty of die area. But when you talk about embedded flash and MEMS, that’s a lot to carry the die along when you’re only using 2% for that extra capability. From a technology standpoint it can be done, but the cost of that silicon isn’t worth it.