Experts At The Table: Stacked Die And The Supply Chain

Second of three parts:Starting points for stacking; where standards are needed; 2.5D vs. 3D stacks; the role of test; the challenge of interconnects; potential power shifts in terms of who’s in control.


By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis at Tessera; and Sashi Movva, strategic sourcing specialist at Qualcomm. What follows are excerpts of that conversation.

SMD: What’s driving the push toward 3D stacking?
Baldwin: The customers have a function they need to get to market. They’re integrating for power. They’re integrating for area. They’re also integrating for cost. They come to us with a problem and say, ‘Help us get this solution to market.’ Part of our solution is going to be standard design services. Part of it could be in the form of a die library, which is a menu of tiles. Die libraries have a lot of promise. You have building block functions that are captured at the die level with industry-standard TSV spacing, test methodologies—all the things that allow us to make a Lego building-block stack out of disparately sourced devices. This is a good idea. It’s difficult with today’s technology.

SMD: That brings up an interesting point, which is exactly what we mean when we refer to stacking. We have memory, memory on logic, and 2.5D stacks in a package. For each the problems are different. Where do we start?
DeLaCruz: Those are different solutions to different problems. A 3D stack is going to be very small and compact. Putting lots of large die together in a 3D stack is not going to make a lot of sense. There will be a lot of reasons for 2.5D, though. If you do the math, it may be less expensive to do a 2.5D solution than to make one large monolithic solution. From an NRE risk standpoint, re-using tiles that are proven and well-known will reduce the risk. The only reason that people go to 28nm or 22nm is they have one or two IP blocks on there that require going to that smaller node, whether it’s memory or the processor. Once it’s done and proven out, it’s likely that everything else can be done at a lower-cost node. Being able to put things together in a larger area space is where 2.5D will have its sweet spot. It will be a lot less expensive. But the 3D arena is more of a space-constrained environment. Having very high-powered devices in a 3D environment is not going to work out too well. It works very well in the mobile market where space is important and low power is the key.
Movva: From a technical aspect, 2.5D addresses the mechanical reliability and thermal aspects. You don’t have to directly characterize the effects of the vias on the node due to the interposer.
Baldwin: The idea of an interposer sounds very evolutionary from today. Just like we’re using package substrates for multichip modules, we can use an interposer inside the package and gain greater density. But now your tools can’t fully model the electromagnetic effects of a through-silicon via. How you’re going to handle that is to space off at first so there’s a do-not-use zone around each via. But you have an interposer, which doesn’t have a ground plane, so now you need coaxial-type TSV structures going down into the interposer and asserting some sort of electrical level. And now you have a large area that’s do-not-use, and you ask all your providers of these die libraries who is willing to make their die less optimal so it gains this potential of use in a 2.5D or 3D package? Who will increase their unit cost to support this potential function?
Woychik: Talking with the users, everyone agrees 3D is the way this is going to go. But getting there will be non-trivial. It’s a big job because you have to look at ‘keep off’ zones. How do you come up with a design tool to lay out the TSV. This is where the 2.5D silicon interposer plays a good role because it provides a useful means to get there and it’s a good learning tool. The classic case we’ve all been hearing about is the Xilinx Virtex 7. The main driver for that is how you get a large die that yields sufficiently. They’re able to yield smaller pieces that integrate on silicon substrate. That gave them about 95% of the performance. That was a major enabler. At the same time, it helped drive the interposer technology. To do that in a 2.5D device is non-trivial. You take baby steps before you take the big one, and that will help drive the total 3D solution. Meanwhile, we see 2.5D won’t go away.

SMD: Is there any standardized way for testing 2.5D chips?
Pateras: You can apply some of the 3D approaches. Typically you don’t need them in 2.5D. With 3D, Imec has developed a test elevator concept because there’s no accessibility to the die that are stacked. You have access to the bottom and top die, but there’s no access anywhere else. So you have to use TSVs to get from one die to the next. With 2.5D, very often the die you’re placing on an interposer have access to the outside world. There’s less of a need to create a complex infrastructure for access test resources like built-in self-test and scan chains.

SMD: This industry has had mixed results with standards. The dueling power formats are a case in point. Will we able to move with standards in a stacked die world and have we really learned any lessons.
Movva: There is a lot of momentum that started several years ago in standards for design, manufacturing and even handling. The handling is going to be critical when there are multiple companies involved. But all of that is needed to enable the 3D supply chain. We would like to see that momentum continue.
Pateris: I’m optimistic, particularly in test. If you look at history, we’ve tended to narrow in on some well-adopted standards for test. Going back 20 years, we combined various chips at a board level and developed IEEE 1149.1 and the JTAG (Joint Test Action Group) standards. There are only a couple standards being developed for 3D and there are contributions from all the major players. My feeling is they will be successful.

SMD: How good or bad will the effect of disaggregation be on stacking?
DeLaCruz: The various different standards for test and wafer handling are moving. But there is nothing dealing with the interconnects. You didn’t really have to worry about those before because everyone could handle their own stuff as long as they could fit it into a package. But to design one of these tiles to go into a 3D tile is not the same as you would design the interconnect to go into a 2.5D structure. In 2.5D you don’t have your signals on all four sides because it would require using too many layers of an interposer to route them all over. Dropping the cost of the interposer by reducing the number of layers is very important. The number of layers in an interposer is a big cost savings. Planning out these tiles ahead of time is important. But will the design of a tile be for the 3D space, where interconnects are over the entire area, or with 2.5D where the interconnects are mostly on one or two adjacent edges. That’s where I don’t see any standards.
Baldwin: If you look at the foundries and their business model, 3D is a clear inflection point. They have to maintain enablement. People that want to bring them business have to be able to do that. We can’t ask all the customers to take on 3D chip design. It’s something where people will need a concrete definition of what the chip needs to do and then a way to get it developed. That exists today in the digital realm. They can go to partners and get that implemented. Those two worlds are going to meet. We’re going to have companies whose role is to take the solution from the customers and take the enablement models that come out of the foundries and put the two together. So there will be a huge push from the ecosystem to make that happen. That will require standards and modeling. Currently they’re all working on drilling and filling, but there’s a lot more to come.
Woychik: This gets into the integration. It can’t work in a disaggregated environment. It has to be fully integrated. That’s where the packaging house can play a very important role. That’s where it can all come together. You’ll get into standards for design, test, how to lay out the die. And who’s going to make it? The packaging house. The package will drive the solution to get to the end customer. That’s why you’re seeing a close alliance between the packaging house and the IC fabs today. They both need each other.

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