Experts At The Table: Building A Better Mousetrap

Second of three parts: Re-use of parts now raises issues of power consumption; some tools still missing.

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Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at Atrenta. What follows are excerpts of that conversation.

By Ed Sperling

PD: Some of the suppliers of IP have eliminated a low-power version because they assume everything will be low-power in the future. Is that the norm?

Allen: It’s a question of how much time the IP supplier has put into trying to reduce the power. There’s a large body of IP where it’s designed as one monolithic thing, but very often when it’s put into an SoC the whole thing can be shut off.
Zarr: A lot of the IP is on a block, so you cannot dynamically scale it down.
Subramaniam: Some of the IP also relies on a certain level of voltage. You cannot indiscriminately lower the voltage to lower the power. Analog blocks need a higher voltage for noise margin and all their special requirements. Memory is another one of those. Every process has a VDDmin associated with the bit cell. You cannot expect the memory to work below that VDDmin. At best you can split the memory into two power domains and have a power domain for the bit cell and another for the periphery. But these things make it more complicated. If all of this increases the complexity by 100% and increases the risk of not meeting the schedule, I’m going to be reluctant to implement it.

LPD: How real is the risk?
Carlson: A lot of the risk is perceived risk. Faraday did a study where they took out 20 chips of increasing complexity with some analog content mixed in. They found they were actually closing faster using some of the advanced automation techniques for low-power designs. Doing a big SoC is complicated, no matter what. Adding another power domain doesn’t double complexity. What people have to do in power grid design and analysis is already hard. You have these analysis loops and you’re specializing in power. There’s plenty of experience behind this to say, ‘It can get done and it can get done efficiently.’ It’s the people who haven’t done it who say, ‘ I don’t know how to do it and I don’t know what the impact is going to be.’ And by the way, it’s 2008 to 2009, and I’m not going to do anything that increases risk. No manager is going to put their program on the line with something they’ve never done before for an unknown benefit.
McDonald: My customers push that problem down to the implementation side. They’re worried about pulling enough of the system together to accurately characterize the workload. Using large blocks of IP is a good example. One of the customers we dealt with recently had a large graphics processor. They had designed it and it worked great, but they couldn’t use it in the SoC because it killed the power consumption. They didn’t have the modes available to control it and turn it off when it wasn’t needed. The guys who designed the graphics processor had no idea how this thing was going to be used. They needed to have the foresight to put in the controls to be able to turn it off.

LPD: So that graphics processor was being designed for multiple applications?
McDonald: Yes, and if it has multiple applications how it needs to be designed from a power perspective is completely different.
Carlson: I agree. You need to be overlay different power structures.
McDonald: If you can overlay those using the same core function and changing the power characteristics, that becomes very valuable. But the tools aren’t there to do that today.
Allen: The modeling languages aren’t quite there to do that today, either. An IP supplier may have in mind several different ways to configure the power strategy, but a user of the IP can’t come along and arbitrarily impose their own. They don’t have enough information about what the IP actually does. If analog is required to maintain a certain voltage, and a processor designer or IP supplier knows there are three different blocks that could be independently powered, they need to be able to present a menu of the available ways to configure it. Both CPF and UPF are starting to represent that as a list of possible configurations.
Carlson: It’s an orthogonal purpose. You may want timing constraints and power constraints to go hand in hand.
Allen: Right. So what are the possible different ways these things can be configured? The IP suppliers have been requesting this, and they’re driving these IP standards in that direction, but they’re not there yet.

LPD: Is there a minimum amount of battery life customers are asking for?
Zarr: There are two requests we see. It’s not battery life in particular. They’re looking for other things in handheld devices. One is thermal management, and they’re running out of vehicles to do that. Battery life is part of that. The other one we’re seeing, which is even bigger, is total power dissipation. In infrastructure types of applications, where there’s a lot of processing power, people are hitting the limit of how to get the feed out of the device or the current in. There’s also legislation being pushed for data centers to get power consumption down. They’re running out of simple approaches, so now they’re looking at architectural approaches to say, ‘What can we do to redesign what we’ve done in the past to lower the energy?’ One is frequency scaling or clock gating. What’s interesting is it’s not as much of an issue with the small handhelds as the larger power consumers.
Allen: The middle of the spectrum doesn’t care as much. It’s the low-power and high-power guys who care.
Carlson: What we see, irrespective of where they are on the spectrum, green is competitive. I haven’t talked to anyone doing 65nm or below who doesn’t care about power. Some of that can be mitigated just by going to a low-power process.
Allen: The corollary question is whether anyone would delay their tapeout if they didn’t meet their power budget. A lot of people say, ‘No.’ They’ll delay for timing, but if they had a 2-watt power target or a 10-watt power target and they knew they were going to miss it, they would still tape out.
Carlson: This is an area that really needs improvement, too—the way the specs get done. In timing we have to meet the specification. In power, it’s 50% or more. There’s a printer company that didn’t meet the envelope, so they added in a $1 heat spreader. That’s 50 million units, but when they got the chip back they found out they didn’t need the heat spreader, so they wasted $50 million. It’s overdesign. We used to have this in performance. Now we have it in power.
Subramaniam: People only think about timing and performance as their No. 1 goal. Power is never considered a primary goal in any design. We see the problems more on the high end of the spectrum. At the low end, most of these handles can be turned off, so leakage power is the problem. At the high end, you don’t have too many choices about turning off portions of the chip. In supercomputers, graphics accelerators and telecom chips, performance is the No. 1 criterion. Power is secondary.
Allen: The low-power design guys have been dealing with that. At the high end of the spectrum, they’re just starting to deal with green laws and the cooling problems in data centers.