Experts At The Table: Challenges At 20nm

By Ed Sperling
Low-Power/High-Performance Engineering sat down to discuss the challenges at 20nm and beyond with Jean-Pierre Geronimi, special projects director at STMicroelectronics; Pete McCrorie, director of product marketing for silicon realization at Cadence; Carey Robertson, director of product marketing at Mentor Graphics; and Isadore Katz, president and CEO of CLK Design Automation. What follows are excerpts of that conversation.

LPHP: It looks doubtful that EUV will be ready at 20nm or even at 14nm. What happens after that?
McCrorie: Once you get past triple patterning it becomes unreasonable to manage. The question now is whether EUV will come before we get past triple patterning. We’re trying to manage right now with triple patterning. We’re looking at 15nm and 14nm right now to make sure it’s enabled, but we don’t know what will happen. Beyond triple patterning I would question whether it’s even viable to go there.

LPHP: What are you looking at beyond that?
McCrorie: I can’t talk about that right now.
Geronimi: There is a lot of uncertainty. It’s clear there is investment in EUV. Until EUV is ready, though, we will be using multipatterning.

LPHP: But won’t signoff be really drawn out as a result?
Geronimi: EUV is just better photography.
Katz: People are working out solutions—everything from simplifying layout, reducing the number of transistors that are designed at any one time. There are techniques being applied right now within the current paradigm to increase reliability for double patterning. Those techniques can get extended to lower feature sizes. There’s a race right now between the big equipment manufacturers to add something that can write at the next dimensions fast enough to satisfy large-scale commercial production. There’s a lot of money at stake in etching the next generation feature size.

LPHP: Assuming we do get this solved, we still have a lot more real estate and complexity on SoCs, cores running at different speeds and different voltages. What do we have to do from a design standpoint?
Katz: We always talk about system on chip with a notion that we are integrating discrete systems. What we’re now doing is entirely new generations of systems getting put onto a single die. You won’t see people increasing clock speed, so all the improvements have to be in architecture. These will be extremely complicated systems with lots more function. That said, the tool flows that have been constructed are very brittle. The amount of scripting around each tool and flow to make them work is enormous. In most cases, the people who wrote those scripts aren’t in the same jobs anymore. The tools flows aren’t really amenable to lots of change. When you talk about the IP that goes onto a chip, and then you layer in things that are more innovative for dealing with multi-mode, multi-corner, as well as what is a signoff flow, that’s when it becomes very complicated and expensive. Everyone wants an evolutionary improvement in their flows that accommodates radical changes in physical layouts. Those things don’t fit well together.
McCorie: The guys who wrote the scripts are still the same guys writing the scripts. None of those scripts are being supported by novice engineers. They know the ins and outs of them. There will be scripting changes required. I agree with that. Are they the easiest scripts to use? Probably not. The most advanced customers are used to dealing with the newest technologies. For the average customer, that’s not the case. I do agree there are problems with the scripts, but they’re a necessary evil. And they’re certainly maintained by the right people.
Katz: There is a whole spectrum of scripts. For the people doing the A15 core, they’re absolutely updating them. For other shops, there are legacy scripts. The person who wrote them may or may not be there. But it’s not just a script. It’s the whole complex stack, from the system-level description all the way through the layout.
Robertson: At 20nm, there are no average customers. These tools do need to work well together, but they also need to work in a way that non-average customers can use to create designs with their IP and their best practices. That’s why the scripts were started in the first place. That was their value add above what Mentor or Cadence could provide. But they’re not providing that framework to the world. There’s a careful balance between automating the tools and still allowing flexibility with custom scripting for an advanced customer.
Geronimi: There are a number of customers with advanced technologies. At the beginning it’s limited and unless they’re doing something generic, it’s not very useful.

LPHP: Can you develop enough consistency between one chip and the next to have faster time to market and faster signoff?
Robertson: There has to be flexibility on top of the tools we provide. For all of these customers, they’re going to go to a handful of foundries, which have a consistent design rule manual and a consistent SPICE rule manual. Unfortunately for these large customers, which are used to getting a lot of attention, the design rules and the amount of physical flexibility that is possible is narrower and narrower. There are restrictive design rules, certain ways you can lay out your transistors, and potentially even more restrictive rules when we get to finFETs. So their hands are being tied more and more, and the tools need to adhere to what the foundries say they can manufacture. Then in terms of the design flows you can always tweak that, but there are going to be best practices that can be proven out. We need continue to innovate and better integrate the tools. Within one company’s tools and across multiple companies, the tools are brittle. But we will be providing layers of flexibility so a customer can integrate their analog IP onto digital IP, which is fairly consistent from one company to the next.
McCrorie: Looking at the different foundries, there’s not a radical difference between them at 20nm. They’re all using the same kind of equipment to do this stuff, so they’re putting the same jigsaw puzzle together. We get requirements from multiple customers. Customer A says one thing, customer B says another, but you find out eventually that they all want the same thing. It’s part of the normal maturation process. Then you still have an overlay of IP where individual customers have something that differentiates them.

LPHP: What are the biggest problems ST is facing?
Geronimi: We need to look at what’s been addressed and what still needs to be addressed. The big problem is power—reducing power. There are different ways to do that. One way is fully depleted SOI to get to the next generation of transistor. The rest is around double patterning. Because we are close to the technology we have a good understanding of the physical effects, but it still takes time because you need to experiment in silicon.

LPHP: Can you still do engineering change orders at advanced nodes?
McCrorie: If we continue doing ECOs the way we do them today, no. It’s too complicated. But the EDA industry is focused on automating as much as possible, so as new challenges come through that causes innovation in the software industry, which helps ECOs go through more smoothly. DFM needs to be brought in. It will be a whole new flow that we have to work on.
Katz: People need to think through the incremental flows. You can’t get there from here today. As we go into 20nm and 14nm, the corners are exploding. There are temperature, process, voltage, and all the different modes and metal corners. You have a very large number of—in some cases 100-plus—signoff corners today.