Experts At The Table: How To Improve IP Quality

By Ann Steffora Mutschler
Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of IP portfolio marketing at TSMC. What follows are excerpts of that conversation. For Part One, click here.

SE: Can we expect a standard level of quality with IP today?
Rowen: I actually think it is possible to achieve a standard of quality in IP that transcends and goes across many different forms of IP and it really goes back to sort of an old principle of quality which is you have to have a process. It has to be a well-established, documented process. You have to be able to show that you’re following a process and you have to have a feedback loop to ensure that process is appropriate to the different kinds of deliverables that you create. This was one of the biggest transformations in quality within Tensilica as we established these processes and could formalize them to the point at which we could let our customers audit what we were doing. We were able to sit down and talk about what we did as we walked through the development of some product. There’s a whole set of things we discovered along the way. In fact, we didn’t have a classical hardware quality issue at all. We had developed from early on a culture of, I would say, obsessive paranoia within the hardware development team and they were extremely good at figuring out what is it they were trying to do, what were the appropriate tools to enforce it and how to test and deliver it. However, there are so many other forms of deliverables and so many different kinds of issues that come up with customers that we recognized that we needed to expand our definition of what we needed to do. There are some unheralded dimensions of that quality process which are centrally important. One of them is communication; communication between the customer and the vendor on quality issues because customers are going to have questions all the time. In course of integrated or using some piece of IP, a question is going to come up…You certainly need to make sure that there is a process by which this communication is tracked and there is closure on these issues. Most of the things that customers suspect are bugs are not bugs at all. They are misunderstandings.
SE: It’s just functionality that they don’t understand.
Savage: It’s a gap in understanding.
Rowen: They are not applying it in the way it was intended, the documentation was not sufficiently clear. They did something to it along the way. There are lots of possibilities but they are all equally seriously in the minds of the customer and it is incumbent on the vendor to do whatever is possible to help them through whether it is a hardware bug or not. There also are bugs that do happen very occasionally, thankfully, but there needs to be communication about those things. It’s a recurring theme – the thing that a user of IP hates most is they discover a bug, they go back to the vendor and the vendor says, ‘Oh yeah, I knew about that.’ Nothing boils the blood more than that.

SE: Are all IP vendors following this kind of rigorous process?
Matter: If they are still in business. Part of it is almost Darwinianism at its finest. The community of IP users and the IP community itself and the people that [say], ‘I know if I’m evaluating Tensilica’s IP, I first have looked at any lead vehicle evaluations that have gone on in my company in the past and then I’ve also talked to all of my other support and vendor partners and there’s a quiet whisper among the community of who to trust and who not to, and who is responsive and what you do about it. And within that community, your integrity is key. The communication aspect is key. I’ve seen a lot of claims from these folks and I quietly sit with reservation about those claims because I may have working familiarity with it. I don’t think you can hide. Obviously I think the transparency is great, but really what Chris alluded to, which is really key, this is attached to a continuous vigilance – you have to be always running continuous regressions back on your IP, you have to be paranoid to the max to where you’re really looking out for the interests of your customers because they are looking to you to maintain that quality. It shouldn’t be incumbent on them.
Savage: One thing that’s improving is the sophistication of our customers – it keeps rising. Back to your Darwinian point, if your customers become more sophisticated than their suppliers, it’s a big problem for the suppliers. You have to be in the lead of your customer at all times. All of us as IP providers have to be on the leading edge of what’s going on because we have to be at least one step ahead of our customers.
Matter: That’s a funny thing. Juxtaposed against that there’s a claim that there was a hollowing out of expertise among customers where actually they’re looking for, let’s say with the handset manufacturers or system suppliers, not the SoC guys, to where a lot of the R&D and verification is actually done by the SoC – and now incumbent in that partnership – is the IP supplier because there should be actually no distinction. I’m giving you a solution and I don’t know all the things that went into your part, and frankly I don’t care. But what I do care about is that you’re going to deliver to me a complete solution and for very large SoC companies, they do a majority of the R&D because the margins are razor thin on a lot of products, whether they be phones, or whether they be PCs or tablets, and as the technology curve just races up, and the volumes start to increase, you get that squeeze. I think that’s why it really has to be a partnership between the EDA and the tools vendors, the IP supplies – it’s a continuum. There shouldn’t be little compartments or pockets because at the end of the day, the system manufacturers are looking at that as the complete solution.
Kochpatcharin: From the foundry point of view, we would like to have as many new IP vendors as possible because there are always new ideas. As you look to some of the new vendors, there is no process. They have good ideas but their process is not there. To us, process is also important so we try to come up with standards so that they have a methodology to follow to develop their IPs, what kind of documentation flow, how to do quality improvements and so on…We also have an audit teams so all the IP partners, every two years, we will send a team down to audit them and audit their process – how they do quality control, how they do documentation, how they do testing so our customers have good understanding of what they see.

SE: In spite of that, do you still see some IP vendors that make the same mistakes over and over?
Kochpatcharin: It’s pretty rare now. Those guys who make mistakes over and over won’t be in business.
Sancheti: Dan touched on an import point. They want to foster a bigger IP ecosystem. I think most of the semiconductor companies that we talk to want to see that happen. In this day and age, differentiation doesn’t necessarily come from everybody doing everything. Differentiation comes from using standard parts and then adding your secret sauce on top of it if you are a chip or system company. The fact that big semiconductor companies and foundries drive this process creates that awareness and raises the bar to Darwinian point – you have to force that awareness on the users. The second thing I think TSMC has done very well is articulate very well is articulate the process that they are going to measure their IP vendors with. So if the semiconductor company can articulate the process, ‘Here’s how we’re going to look at your quality,’ now you’ve communicated to them where is the bar. That drives the IP vendors…where they basically not only talk about the process they followed internally for IP development but in the end, they sign off the IP to TSMC’s established standard to make sure that not only was the process complete but in the end, what they delivered to the end customers is what they said they were going to deliver.

SE: Is IP truly portable between foundries?
Rowen: It depends so much on the nature of the IP. The difference between a PHY and a processor, let’s say, is enormous. Some analog block, something that’s built to the specific transistors is built so much on the precise conformance and knowledge of the models of the transistors coming from that particular foundry – and not just the foundry but the infinite detail on that process variation. Whereas, higher level soft IP like processors makes very generic assumptions. In our case, we assume there exists a standard cell library and there exists a synchronous, single ported read-write RAM – that’s all you need to assume about what exists in the library on a given foundry. That said, customers don’t just want to know does it run in this foundry, they want to know exactly how fast, how much power, what size – and that actually is quite dependent on the specifics of that particular library. So while what we deliver as a processor is completely portable, you could run it in quarter micron, you can run it in 14nm finFET without any modification to our deliverables but we do exhaustive characterization across all of the process libraries as well as all of the tool flows that we can get our hands on so that we can answer the question as reliably as possible exactly how fast, how big, how much power is associated with it. Certainly it’s easier than the job of the poor, hard IP maker who has to sweat the specifics of functionality and we don’t worry about functionality in these different processes. We do trust that a NAND gate is a NAND gate and I think it’s generally been uniformly true but it does affect this process dependence.