Experts At The Table: IP Integration Hurdles

Last of three parts: IP platforms, using the right tools, the impact of 3D stacking, what doesn’t work and where the opportunity is for tools vendors.

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By Ed Sperling
Low-Power Engineering sat down to discuss IP integration issues with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys’ Solutions Group; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversation.

LPE: Is a fully integrated IP platform an effective way of dealing with power?
McCanny: There are a lot of issues that we’re still trying to get our arms around. A lot of the tools we’re using were not designed with power in mind. We’ve adapted them. We’re using different constructs to handle power constructs. As an industry we haven’t designed from the bottom up for how power is managed and modeled. Platforms may help, but that won’t be a complete solution. There are still a lot of complex issues to be worked out, such as predictably modeling power. We also need pre-set rules for IP for what you can and cannot do with it. We need to know, for example, ‘This is how IP will behave when you power it up and power it down, and when you go from this voltage to another voltage.’ Right now we’re tweaking as we go along. You don’t know what the IR drop will be or how it will affect the IP block. You have no control over how the power supply is connected to that piece.
Rajendiran: We start somewhere in the middle. There are high-level system-design tools, and meanwhile there has been an explosion of nuances on the physical side. System-level design can be perfect, but then somebody has to map it to a physical and implementable device. If I had a set of functions I want to implement, I could choose hard IP from Supplier A and Supplier B. Each will have a different implication for power. Even where you put it will have different implications. One may cause a different IR drop than the other one. System design has not taken off because you need to know all the possibilities. There are gaps in between.
Gianfagna: Gaps are the enemy. You need everything to be implementation-aware all the way through the process. If you look at the high-level ESL companies that don’t exist anymore it’s because of those gaps.
Brock: A well-defined piece of IP differentiates on power, performance and area. But it also has to be usable. In the case of memory, you have to have a mesh across the whole thing so when you tack on the power you don’t get an IR drop all the way on the other side. If it’s from a reputable vendor you may not have to look inside because you know what it will do whereas if it’s coming from someone else you might have to poke around inside. The only way you know if something can be dropped in from outside the box is by making a lot of mistakes and coming up with something that has been tested over the years and that you know you can trust. So Vendor A may be thinking about all of these little details.
McCanny: There is a lot of IP that’s a black box. To some extent you want a black box, but when something doesn’t work out there’s very little information to determine what the problem is. Knowing which things have been checked out and which things have not is essential to know. You get the numbers but no information about where this data came from. The IP vendor doesn’t want all their secrets stolen, but if the customer uses it in the wrong way there’s no information about why his model doesn’t match transistor-level simulations or his silicon, which is even worse.

LPE: As we move into 3D stacking that becomes even more critical, right? You have proximity effects in multiple directions. How big will this problem be and will it affect 3D’s adoption?
Gianfagna: 3D will change the market. Now you’re not just selling hard or soft IP. Now you can start to think about selling pre-characterized slices in the stack. That could be a memory supplier or an FPGA supplier. It will expand the market. But there’s a new set of analyses. The early analysis of the stack before you place IP becomes much more difficult. You’ve got placement problems and thermal and mechanical issues that didn’t exist before. Making silicon paper-thin and then punching holes through it and seeing if it still works isn’t simple. Beyond that, there’s a whole separate issue on sourcing and building the stack. Who’s going to be the general contractor? Who’s going to take the yield risk and the inventory management risk of the heterogeneous stack of silicon, put it together and ship it to an end customer. The end customer won’t take that risk in every case.

LPE: How much of the content changes in a 3D stacked die and does it come from more or fewer vendors?
Rajendiran: The first place it will really be adopted is in the memory space. The industry is waiting for some standardization of the interface from companies like Micron. Once that happens it’s really going to take off. Meanwhile, whether it is TSV-based or SiP-based, the inventory management issues are the same. We have a customer looking at the SiP package, bringing their die and their partner’s die and we’re putting them together.
Brock: We’re still putting everything together, the foundation IP with memories and high-speed interfaces. We have an analog component, processor component, cells and MDM, so the natural outbreak is to come up with IP subsystems. If a company needs an analog front end for a high-definition TV, we have all this stuff that can go into that. That’s going to be the natural outgrowth of collaboration. At Virage we had a processor, memory and logic, which is what you need to build a core. You can characterize that, add some software stacks and you can start growing them. But you also have to be very cautious about how you build those. You have to be sure there’s a market.
McCanny: When you put all these blocks together you get one big block.
Brock: Or a collection of blocks that can be, ‘Slot A, tab B.’
Gianfagna: The derivatives are a good argument for an IP company being part of an EDA company. You have to have the ability to do customization. A large EDA company can do that. A small IP company cannot. You need infrastructure to do that right.
Brock: There are places for small IP companies. Most of them started as design services companies.
Rajendiran: And most of them still are design services companies. If you look at the IP industry the biggest one is ARM, the next biggest is Synopsys, and after that it’s MIPS. After that, I can’t think of who’s fourth. On the one hand, everyone is a design services company. When this began the only master they served was an OEM company. When it became a completely open market one design served 100,000 companies, so you had 100,000 masters. The IP industry takes the easy way out by remaining small.
Brock: But there are a lot of unique collaborations going on.

LPE: Don’t all the fabless companies become IP companies?
Gianfagna: Is it IP aggregator or creator?
Rajendiran: They do create their own IP that becomes part of the chip.
McCanny: Over time, will the small guys wither away? Will end companies still use the IP from these companies if the IP isn’t completely validated?
Gianfagna: If we can come up with a language for how to do that, then we will use their IP. Validating a piece of IP generally is easier than building it from scratch. If nothing else, you’re on the back of the 10 guys who came before you. The problem is there is no way to validate the quality, the deliverables, the use model, the scope of use and the integration risks.
Brock: Very often it’s a bunch of guys in a garage with a great idea. But it’s how you build it and the methodology. The kind of people like things done and if it’s not done in a certain way they get upset. You need a bunch of those people.
Gianfagna: Strong, rigid methodology pays off in IP.
Brock: It’s this discipline that has to go in step by step. The gotcha is when you skip a step. You may not find out about that for a couple of generations. You need tools to go in and understand what’s really there.
Rajendiran: A lot of people leave companies and that step you skipped a couple generations ago no one remembers. If you can build tools that can probe the IP who’s going to let that happen?
Gianfagna: There are a couple of 900-pound gorillas that could make it work. The end customers also can demand it. The IP providers won’t wake up tomorrow and say they’re open to criticism and change. It’s not just the syntax of the IP, though. It’s power, the clock and other things that do affect the implementation. What they’re trying to do is to dig deep enough to tell their customers what’s good and what isn’t.