Experts At The Table: Obstacles In Low-Power Design

First of three parts: The need for consistent tools and views; tradeoffs with performance; low-hanging fruit; the effects of “finification”; new design approaches.


By Ed Sperling
Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation.

LPHP: What are the main obstacles to lowering power in designs?
Clark: I take other people’s RTL and turn it into GDS II. In doing that, we use half a dozen different EDA tools. We really struggle with the unification of power intent and modeling. Getting accurate models consistent across tools and views is a huge struggle.
Venkatesh: Low power comes at a cost—typically performance. There should be a clear picture of tradeoffs. The other big piece in low power is that there is no clear link at various design stages. There is the architectural level, the TLM level, hardware and software, RTL and gate. You need good models at each stage, and you need to know at these stages what art the tradeoffs. So if you’re doing floating point computations, you need to know the cost of doing two digits or one digit. We don’t know what the difference in power consumption will be. Up to some point you should be able to have tradeoffs for power and also performance, and later at the RTL level onward you need to know how far off you are in terms of correlation to silicon. Power modeling associated with power measurement at each stage is very important.
Wang: From my perspective there are no obstacles. It depends on where you want to go. There are people pushing the power envelope today that no one could even imagine 10 years ago. Human nature will push that even lower, which will require innovation in process, tools, and design circuit techniques. All of these elements need to come together.
Trihy: There are three parts of this. One is the enablement from EDA vendors, and we see a lot of that available today. There are CPF and UPF. Liberty has many techniques for modeling different kinds of cells. Then there is the circuit designer. We will begin to see more circuit innovation. One example is resonant clocking. As the frequencies increase above 4GHz, it makes more sense to put clock meshes on the chips. You’ll see much more focus on accurate inductor design. There will be new techniques. As a foundry, we have to provide a value for customers to migrate to our next offering. There you’ll see the advent of the finFET. Today we offer a 20nm process. We call it “finification.” If you “finify” a design you can see a 40% to 50% reduction in power. All of these are moving in tandem and they’re all achievable.

LPHP: Is power the biggest problem we face going forward?
Trihy: It’s not problem No. 1. You’ll continue to see power, performance and area. We trade them off against each other. At the foundry we build flows for maximum performance, minimum area and best power. They’re so interrelated you can’t just pull one out.
Wang: I have a different opinion. Power is more of a problem than the others. In the last 10 to 20 years, there has been a lot of effort devoted to performance, but we have left a lot of margin on the power side. Why do we keep Vdd at 1 volt? There’s no point. You can drop Vdd to 0.3 or 0.4. People need a safer way to do circuit design. We have a lot of room for improvement there. But looking into the future of platform-based design, we are squeezing more and more functionality on silicon. There is a limit to how many cores you can use. We cannot go beyond a certain frequency—about 2 to 2.3 GHz. Gary Smith predicts that for embedded processors it will stop at 1GHz, with additional throughput from multicore architectures. The reality is that we are reaching the limit of performance. As a result, power will be a higher priority going forward.
Venkatesh: Power management is the No. 1 problem. It’s more related to energy, which is the biggest challenge. There are so many techniques to deliver on performance, but each time power is a problem. In mobile computing, there is a lot of idle time. You can deliver the performance with many cores, but you hit the power budget right away. New techniques are being considered for performance. One that’s being worked on at the University of Pennsylvania is called computational sprinting. It’s based on dark silicon, but when you need enormous performance they turn on all these cores. But they don’t stay on too long because that generates too much heat.
Clark: Power is a big deal, but it’s not very visible to the people implementing the functions. They leave it for the people implementing the structure. They figure, ‘You’ll turn off the right island at the right time.’ It’s a division of labor problem. A lot of our cell coders don’t think about power. It is a challenge, and it hits everything. It affects design for manufacturing, design for test, implementation, all the EDA tools. It touches everything you do. Maybe getting to the lowest power possible isn’t critical. But having a strategic power implementation that works and is testable and still performs the function you intended is a huge challenge.

LPHP: Is all the low-hanging fruit gone?
Clark: No.
Venkatesh: There are a lot of great techniques used by mobile companies that are not easily used by other companies, such as the creation of power domains, voltage scaling, DVFS.

LPHP: But is that really low-hanging fruit?
Venkatesh: It’s at least well understood by the mobile companies. You have to make it more commonplace.
Clark: There’s a small fraction of the chips being manufactured that really are bleeding edge on power management and power architectures. Everyone else thinks, ‘When it gets easy enough we’ll do it.’ The techniques aren’t new, but getting the broad adoption of it is still low-hanging fruit.
Wang: It depends on where you want to go. If you can sell a chip for $1 at 1 watt, why do you need to get it down to 0.8 watts? Economically it doesn’t make sense. The architect decides how the power goes, but you have to sign off on it. The cost of fixing power at an early stage is much lower than fixing it at a later stage. My iPhone is faster than I need. How fast it refreshes depends on my WiFi link and 3G or 4G, not the computation. Over the next decade there will be more and more integration and mobility. In China they have a new term called T2T. It’s thing-to-thing. It’s the same concept as the Internet of Things. All of those push the envelope of low power. People will find low-hanging fruit when they need to find it.
Clark: We have a lot of pressure for time to market. One of our big events is CES. We have to tape out two months ago to demo something at CES. What falls off is power because it’s not necessary for the chip to function.

LPHP: Does power become a focus of attention at the foundry level?
Trihy: Our real focus is yield, but what does surface is less about power directly and more about margin. We rarely hear about customers directly asking about their power spec, but we do get customers asking for help meeting timing closure.
Clark: It will still work if it uses more power. It will still function in the TV or the phone, even though you might not get your ‘green’ sticker.
Venkatesh: We’ve been hearing some companies dropping functionality to keep within the power budget.
Clark: We don’t always know what’s outside the power budget, though. There’s a measurement problem, too. We drop the clock frequency if there’s a problem.
Wang: Nvidia has a very fancy liquid fan that has save their design. For that application it works.
Clark: If you can plug it into the wall, you have a lot more leeway.

LPHP: What does die stacking do to this equation?
Venkatesh: There will be thermal issues. You can manage timing and placement reasonably well, but the thermal problem is acute. And power and thermal go hand in hand. As a result, your floorplan has to change.

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