Facing Off Against Growing Chip Design Complexity

The semiconductor industry continues to face incredible pressures to deliver higher levels of performance in a smaller area, with lower power demands. From high-performance systems-on-chip for 5G mobile devices and network infrastructure to the radio-frequency transceivers that enable autonomous vehicles and the industrial Internet of Things, today’s applications demand a reduced profile, paired with greater power output. This “downsizing” trend has affected every part of the system, but especially the integrated circuits (ICs) that represent the foundational building blocks.

The industry’s transition from a standard 7nm chip size to a 5nm design has delivered profile and power gains, but this trend also brings challenges. As chip size decreases, the risk of defects and failure mechanisms grows — which means chipmakers now have to conduct more thorough inspections, which is costing them time and money. And we’re not even close to seeing the end of downsizing. With 3nm chips coming in 2022 and 2nm designs predicted for 2024, the engineering risk, and the associated verification workload, is only increasing. While a 7nm chip design is predicted to cost $223.3 million, a 5nm design represents $463.3 million in expenses. That number skyrockets to $650 million for a next-generation 3nm chip design.

With so much at stake — including their brand reputations and long-term customer loyalty — chipmakers can’t afford to get their designs wrong. And, given the pressure for rapid and extreme innovation, they can’t rely solely on post-fab inspections. They have to verify their advanced IC designs and identify any flaws upfront, before significant prototyping and manufacturing expenses are incurred.

Due to advanced layout-dependent effects — we also call them advanced fabrication effects — layouts are distorted during fabrication, which means that custom IC layouts do not fully represent the chip that is actually fabricated. These effects are described in the technology files provided by the foundries — and, for very advanced process nodes, they are insanely complex.

The solution is high-capacity electromagnetic modeling, such as Ansys’ RaptorX, to model the most complex analog, mixed-signal and radio frequency ICs, high-speed digital systems on chip, and 3D-ICs, and to be able to do it quickly and simply enough.

Modeling advanced process features significantly improves the precision of simulation results for IC design, leading to decreased prototyping and production costs, faster product launches, and greater product confidence when chips are installed in demanding applications such as 5G, three-dimensional integrated circuits (3D-ICs), and radio-frequency integrated circuit (RFIC) designs.

With its 2022.R1 software, released in early 2022, Ansys has added new capabilities to RaptorX for sub-7nm process nodes. It models all critical layout-dependent effects (LDEs) to support accuracy, speed, and cost-effectiveness in developing chip designs as small as 3nm, and provides multi-patterning-based extraction of advanced fabrication effects. The tool is color-, mask-, and pattern-aware as it calculates all geometric and electrical parameters of IC designs — including width/space, etching, metal thickness, resistivity, dielectric thickness, and dielectric damage. That helps chip designers optimize resistance, capacitance, and inductance for greater performance and reliability in the most demanding customer applications.

Ignoring advanced LDEs during electromagnetic simulation can lead to significant inaccuracies in critical metrics. For series resistance, calculation benchmarks demonstrate deviations ranging up to 140%, while for total capacitance the deviation can be up to 25%.

Deviations of RaptorX models from reference with (green plots) and without (red plots) modeling of advanced layout-dependent effects. Metrics compared are Rs (series resistance) and Ctotal (total capacitance).

All these inaccuracies can create misleading simulation results, failed tapeouts, a longer time-to-market, and huge additional costs.

RaptorX models all LDEs and advanced CMOS fabrication effects down to 3nm with high accuracy using a Random Walk approach that is powered by machine-learning algorithms. It thus guards against chip defects by supporting early-stage verification for designs on the smallest process nodes, with the most complex electromagnetic effects.

As the world’s semiconductor manufacturers rush to introduce the next generation of 2nm and 3nm chip designs, rigorous analysis and design validation have never been more critical. Interested in learning more about the expanded capabilities of Ansys RaptorX? Kelly Damalou of Ansys delivered a presentation on RaptorX and layout-dependent effects as part of TMSC’s 2022 Online North America Open Innovation Platform (OIP) Ecosystem Forum. It will be available for six months.