Facing Up To RC Delay

Improving interconnect performance and across a die means new challenges. There are ways to solve them, but can they be done cost effectively?


y Ed Sperling
Resistance and capacitance delays have always been someone else’s problem to solve at some fuzzy process node in the future, and for the most part manufacturers and equipment makers have done a wizard-like job of making this problem go away. They can’t make it disappear anymore, though, and beginning at 14nm and beyond RC delay is becoming more than just an annoyance.

The problem shows up primarily in the interconnects and wires, but it ripples through the entire manufacturing process in terms of process, materials and cost. It causes electromigration issues, raises the heat in a device, impacts signal integrity and ultimately pushes up the cost of an entire SoC.

“The back-end RC will be a real problem,” said Jong-Shik Yoon, senior vice president of R&D at Samsung. “It may be a scaling limitation.”

He noted that for all the attention paid to finFETs in manufacturing, that’s just one solution to a multi-faceted problem or series of problems. Solutions are needed in many more areas as the industry moves to 14nm and beyond. And even finFETs will have to change. In addition, the extra circuitry used in guard-banding has begun causing a variety of physical effects that can impact performance, power and noise, and the problems get worse as the industry moves beyond 28nm.

Problem in the interconnect
Until now—and certainly for at least the next several nodes—the copper damascene process is viewed as the path forward in the interconnect world. Copper is deposited into open trenches that are filled with a high-k dielectric insulator. A barrier metal also is required around the copper, to prevent scattering that could occur if copper comes into contact with metal.

Copper replaced aluminum at 130nm because it is a better conductor, allowing features to be shrunk without major problems through 20nm in accordance to Moore’s Law. It is likely that copper will have be replaced by something else at 5nm, according to researchers, although so far there is no agreement on what that material will be. Graphene is one option, but there are problems to be worked out there, as well, particularly in regard to scattering effects.

“The question is how long you can extend copper damascene,” said Mehul Naik, distinguished member of the technical staff at Applied Materials. “From a resistive perspective, how can you get more and more copper inside the trenches and how can you design your materials so you get rid of scattering issues that increase the copper resistivity. It’s maximizing the volume and minimizing the scattering of copper. If we can achieve that, we can extend damascene as far as possible. But that goes back into how you pattern the copper and get the fine pitch, and what kinds of issues you run into when you get a fine pitch.”

At the upcoming International Electron Devices Meeting in San Francisco next month, a major focus of the discussion will involve work being done to extend copper using different schemes.

But process technology is only one part of the problem. Unlike in the past, there is no longer just one thorny problem at each new node. At 14nm and beyond, there are at least several issues that have to be dealt with. New dielectrics will have to be developed as the thickness of the materials continues to shrink.

Lithographic issues also will have to be resolved. EUV has received a lot of attention primarily because it was supposed to have been ready years ago. There are now questions about whether EUV will be commercially viable even at 10nm. That has forced double patterning on the semiconductor industry at 20nm, and it could easily require triple or quadruple patterning using 193nm immersion technology at 14nm.

Multipatterning leads to pattern degradation, though, which is why the industry has its collective fingers crossed that EUV will work, probably supplemented by other technologies such as e-beam and directed self-assembly.

It’s also questionable whether bulk CMOS will carry forward most of the industry. A fairly simple fix is fully depleted SOI, which is being used by companies such as IBM and STMicroelectronics. Intel, in contrast, remains committed to extending CMOS until at least 10nm.

And from a design standpoint, the path forward for digital circuitry is fairly straightforward. When it comes to a host of analog IP, sensors and things like RF and mixed signal processing, shrinking to even 14nm rapidly succumbs to the law of diminishing returns. Too much heat is generated to make the process shrink worthwhile and the cost of developing IP at those bleeding edge process nodes is astronomical, which is why there has been so much pressure to begin stacking die in 2.5D and 3D packages.

R&D work under way
From the foundry perspective, the interconnect issues must be resolved. Greg Bartlett, CTO at GlobalFoundries, said tungsten remains a problem for the interconnect.

“We’re looking at graphene-clad copper as one possible solution,” he said. “A second approach is to look at design intelligence in power distribution. And the third knob we can turn is to stack die in 2.5D and 3D, which really appeals to certain market segments like mobile. But there’s still no magic material to replace copper, particularly for the price tag. And there are a lot of supply chain costs that have to be considered with stacked die.”

Another approach is to creating a self-forming barrier that doesn’t actually occupy any volume in the copper itself.

“To reduce R what you need to worry about the fundamental reason why copper resistivity goes up,” said Applied’s Naik. “There is scattering across the sidewall, across the grain boundaries and background scattering.”

At ARM, which makes processor cores, the concern is resistance in the wires, the transistors and the contacts, because all of those can affect performance.

“For the contact, basically what you’re doing is cutting a hole in the oxide and making sure you don’t touch the gate,” said Greg Yeric, an ARM fellow. “At 10nm and beyond, the space between the gates is too small, so the foundries are moving to a self-aligned oxide. But we are still seeing more resistance and capacitance. At every node, the contact resistance is getting higher.”

A variety of new metals and approaches will be necessary. He said he recently had to look up the element Ruthenium, a member of the platinum family of metals, to look at its properties because it is being suggested as a possible replacement material.

Part of ARM’s concern is also the resistivity in wires. ARM’s entire marketing pitch is centered around low-power processing, and if the wires are too thin and don’t allow the electrons to pass freely enough, even the best interconnect designs won’t solve the problem.

The future
Research across this field is ongoing. The key isn’t just solving RC problem. It’s solving them in an economical way. There are enough possible workarounds to limit the effects of RC, which include performance as well as physical effects and electromigration. But fitting that in with existing manufacturing processes with a minimum of disruption and extra time is key.

“Contact performance and via performance, in that order, are the two areas that need to be addressed to reduce resistance at critical interfaces,” said Applied’s Naik. “The changes we’re trying to make in the interconnect trench will affect the via. The contact involves changing the interface layer thickness to enable scaling on the contact. There is only so far tungsten can take you.”

What will come after tungsten is anyone’s guess. And for wires, adding TSVs or interposers between die in a single package can help. But no matter what route is taken, over the next couple of nodes significant changes will need to be made in a number of areas involving RC. And those changes will likely affect the entire semiconductor supply chain, from design through to manufacturing.

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