Fallback Plans

While the semiconductor manufacturing and EDA tool providers are preparing for EUV at 14nm, they also are examining alternatives.

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By Ann Steffora Mutschler
With EUV lithography missing a few deadlines already, the semiconductor industry has begun to search for alternatives.

None of these solutions is simple, of course, and it’s questionable whether they’re even economically viable. And even if EUV is ready for mass production by 14nm, there are new challenges that have to be dealt with—particularly in the space between design and manufacturing, according to Juan Rey, director of engineering for the Calibre Division at Mentor Graphics.

“EUV brings several characteristics into its process that forces a larger amount of flattening of information,” Rey said. “So even though the designer may have been careful in creating a hierarchical design, the exposure process brings mechanisms such as flare that tend to force flat processing of the design. Improvements in the algorithms to deal with that type of issue is something that is required, and forces the industry to research algorithms and develop algorithms to deal with it.”

Additionally, new models are required to capture the physical shortcomings of the EUV semiconductor process because going to a much shorter wavelength creates new phenomenon and effects that need to be considered. These models impact rules imposed on designers that need to percolate upstream into EDA tool methodologies.

If EUV isn’t ready, then what?
If EUV ends up not being commercially viable by the 14nm, quadruple patterning is a likely contender—at least from a technology standpoint. Economics are another matter.

“Intel sees a clear map to 10 nanometer using immersion lithography, so Intel knows they can get there. TSMC isn’t so sure they can get there,” said Dean Freeman, vice president at Gartner Research. “The memory companies think they can get to 1y using double/quadruple patterning but they are concerned yields and rework are going to be a problem. With DRAM, it’s 20-some-odd-nanometers where they think they are going to hit the wall because their density is a little bit more.”

Mentor’s Rey agreed. “What we are hearing from people in the semiconductor manufacturing side of things is that double patterning can indeed be extended to multiple patternings—triple patterning and other flavors—and then it should be possible to go to the next node.”

Current concerns are not so much about having a technology that can deliver the dimensions that people expect but more about the cost of design and manufacturing.

The double patterning techniques coming into production will bring a new set of restrictions. That translates into new constraints that have to be verified and new modifications that need to be made in the physical layout and the physical design. They key is that it has to be manufacturable—and making that happen will get far more complex.

“The impression that we’re developing is that now that 20nm is going into production and 14nm is in advanced development stage,” Rey continued. “Truly the best candidate seems to be at this moment some form of multi-patterning, even though it’s going to be too expensive. The only hope is that the prices could come down once people learn a lot more about the process and how to design and then there’s a way to make it cheaper.”

This complexity issue with EUV is perhaps the largest cloud on the horizon.

“I think it’s definitely going to impact the complexity of how we get to the specs that we want,” said Joanne Itow, managing director for manufacturing at Semico Research. “It just makes life more complex for everyone in that whole process, but what’s the alternative? We always learn to figure a way of doing it, but what if it costs more than $100 million for an EUV tool? We either spend it on that or on more engineering resources for the design. Either way it certainly makes it more expensive.”

A second option that has been proposed as an alternative to EUV is directed self-assembly (DSA), but it’s not exactly smooth sailing with this technology either. “Unfortunately…directed self assembly also doesn’t have enough maturity to be considered for the 14 nanometer node so it seems that the challenge will be for the following node—for what comes after 14,” Mentor’s Rey pointed out.

Gartner’s Freeman recalled that IBM has been talking about this for more than seven years. “It’s interesting and has some great possibilities, but the problem is DSA is 99.99%. How many transistors do we have on a chip these days? We use every single one of those puppies. We don’t know why we use them or what we are using them for…The problem with directed self assembly is that…it’s only two to three 9’s accurate and so you’re going to have to help it in some way, shape or form.”

A third EUV alternative is direct-write e-beam, which appears to be closer than EUV at this moment and is especially closer if EUV misses another milestone. KLA, Mapper and Lam Research all have investments in this area.

At the end of the day, Freeman said, “When has this industry ever ground to a screeching halt? You’ve got so many blasted smart people working on so many different things that somebody is going to come up with a solution—provided physics allows us to do it.”

Conclusion
Even without EUV, designing semiconductors has been an issue for some time. Often simpler or grid layouts need to be used to reduce the impact of odd and difficult to product shapes at smaller design geometries, said Jim McGregor, principal analyst at TIRIAS Research. “This will continue to be an issue no matter what lithography technology is used.”

In terms of manufacturing, not having EUV is already an issue. “The industry is turning to multiple tricks to extend the life of existing lithography technology, such as immersion and multiple patterning. There are other technologies that could be used, but they are either slower to manufacture or require shifting away from the use of silicon wafers all together, which is hard to do when you have 40 years of experience and trillions of dollars invested in perfecting these processes,” he explained.

Like all roadblocks the semiconductor industry has faced, solutions or workarounds are still in site for at least the next few generations. “After that, we may finally run up against the laws of physics and/or costs that are just too high to overcome,” McGregor said.

He shies away from making a prediction as to when this will occur because every time it looks like it might happen, the industry finds a solution: “Even Gordon Moore has predicted the end of Moore’s Law—twice.”