Fast Parallel Multi-HDL Compiler (UC Santa Cruz)


A technical paper titled “A Multi-threaded Fast Hardware Compiler for HDL” was published by researchers at UC Santa Cruz.

“A set of new Hardware Description Languages (HDLs) are emerging to ease hardware design. HDL compilation time is a major bottleneck in the designer’s productivity. Moreover, as the HDLs are developed independently, the possibility to share innovations in compilation technology is limited.

We design and implement LiveHD, a new multi-threaded, fast, and generic compilation framework across many HDLs (FIRRTL, Verilog, and Pyrope). We propose new parallel full and bottom-up passes to handle HDLs. The resulting compiler can parallelize all the compiler steps.

LiveHD can achieve 5.5x scalability speedup when elaborating a CHISEL RISC-V Manycore. It also gets from 7.7x to 8.4x scalability speedup for a benchmark designed in all three HDLs. This is achieved with a fast single-threaded LiveHD baseline with 6x speedup compared to compilers such as Scala-FIRRTL and 8.6x against Yosys on Verilog.”

Find the technical paper here. Published Feb. 2023.

Wang, S. H., Coffman, H. J., Mayer, K., Garg, S., & Renau, J. (2023, February). A Multi-threaded Fast Hardware Compiler for HDLs. In Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction (pp. 25-36).HDL, Compiler Design, Parallel Compilation.

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