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Verilog HDL And Its Ancestors And Descendants


This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog has completely revolu- tionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. For large-scale digital logic design, previous schematic-based techniq... » read more

HDL Simulation Acceleration Solution For Microchip FPGA Designs


Mission-critical FPGA designs for space and radar applications continue to increase in complexity, such that they require a comprehensive and robust verification environment. There are hardware-in-the-loop solutions in the market that utilize FPGA boards, but when it comes to establishing functional coverage and debugging the custom logic, users would typically need to go back to HDL simulation... » read more

Is Hardware-Assisted Verification Avoidable?


Emulation is emerging as the tool of choice for complex and large designs, but companies that swap from simulation to emulation increasingly recognize this is not an easy transition. It requires money, time, and effort, and even then not everyone gets it right. Still, there are significant benefits to moving from simulation to emulation, providing these systems can be utilized efficiently en... » read more

Week In Review: Auto, Security, Pervasive Computing


AI/Edge The United States now has the highest number of COVID-19 cases, and the state governments in the U.S. are asking technologists for help, according to a story in The Washington Post. Data scientists, software developers, and others are needed to help. New York State started a Technology SWAT team calling for help from the tech community. Intel AI Builder program participant DarwinAI ... » read more

Can Debug Be Tamed?


Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

Formal Datapath Verification


J.T. Longino, formal verification application engineer at Synopsys, drills down into how to achieve confidence in datapath designs by applying formal solvers and methods to data transformation areas of a design rather than the control path areas. https://youtu.be/n1zO3GxEZVI     See other tech talk videos here. » read more

Tech Talk: DO-254


Aldec's Louie De Luna explains the safety critical standard for the aerospace industry and how that parallels what's happening in automotive electronics. https://youtu.be/qa1g1NNVj60 » read more

FPGA Design And Verification in Mechatronic Applications


The biggest challenge in using FPGA devices may be one of methodology. FPGA designers are familiar with HDL-based requirements-driven design methodologies for digital electronics. But how can requirements be expressed for a system that, while it contains digital elements, is fundamentally non-digital? Fortunately an executable HDL exists that extends the capabilities of the digital VHDL languag... » read more

Experts At The Table: Platform-Based Design


By Ed Sperling System-Level Design sat down with Simon Bloch, vice president and general manager of ESL/HDL Design and Synthesis at Mentor Graphics; Mike Gianfagna, vice president of marketing at Atrenta; and Jim Hogan, a private investor. What follows are excerpts of a lively, often contentious two-hour conversation.   SLD: What’s the starting point for designs in this world? Hogan: I... » read more