Chip Industry Week In Review


TSMC is expected to reduce its Fab 14 mature-node capacity by 15% to 20% to free up resources for its advanced packaging technologies, reports Counterpoint. The foundry will likely rely on its VIS affiliate site in Singapore (operational in late 2026) and other overseas fabs to ensure continued supply for older nodes. Memory The U.S. threatened 100% tariffs on South Korean memory compan... » read more

A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)


A new technical paper titled "Memory DisOrder: Memory Re-orderings as a Timerless Side-channel" was published by researchers at University of Washington, Duke University, UC Santa Cruz, Raytheon and Microsoft Research. Abstract "To improve efficiency, nearly all parallel processing units (CPUs and GPUs) implement relaxed memory models in which memory operations may be re-ordered, i.e., ex... » read more

Chip Industry Week In Review


The U.S. Department of Commerce and Amkor Technology signed a deal to provide up to $400 million in funding, under the CHIPS and Science Act, to build a previously announced end-to-end advanced packaging plant. The combined funding is expected to total about $2 billion. The new facility will add some 2,000 jobs in Peoria, Arizona. The SK hynix Board approved its Yongin Semiconductor Cluster... » read more

Chip Industry Technical Paper Roundup: July 8


New technical papers recently added to Semiconductor Engineering’s library. [table id=238 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review


Early version due to U.S. holiday. The U.S. government announced a new $504 million funding round for 12 Regional Technology and Innovation Hubs (Tech Hubs) for semiconductors, clean energy, biotechnology, AI, quantum computing, and more. Among the recipients: NY SMART I-Corridor Tech Hub (New York): $40 million for semiconductor manufacturing; Headwaters Hub (Montana): $41 million f... » read more

Lower Energy, High Performance LLM on FPGA Without Matrix Multiplication


A new technical paper titled "Scalable MatMul-free Language Modeling" was published by UC Santa Cruz, Soochow University, UC Davis, and LuxiTech. Abstract "Matrix multiplication (MatMul) typically dominates the overall computational cost of large language models (LLMs). This cost only grows as LLMs scale to larger embedding dimensions and context lengths. In this work, we show that MatMul... » read more

Chip Industry’s Technical Paper Roundup: Mar. 6


New technical papers recently added to Semiconductor Engineering’s library: [table id=84 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Fast Parallel Multi-HDL Compiler (UC Santa Cruz)


A technical paper titled "A Multi-threaded Fast Hardware Compiler for HDL" was published by researchers at UC Santa Cruz. Abstract: "A set of new Hardware Description Languages (HDLs) are emerging to ease hardware design. HDL compilation time is a major bottleneck in the designer’s productivity. Moreover, as the HDLs are developed independently, the possibility to share innovations in com... » read more

Chip Industry’s Technical Paper Roundup: Nov. 21


New technical papers added to Semiconductor Engineering’s library this week. [table id=65 /] » read more

Power/Performance Bits: Jan. 2


High-temp electronics Researchers at Purdue University, UC Santa Cruz, and Stanford developed a semiconducting plastic capable of operating at extreme temperatures. The new material, which combines both a semiconducting organic polymer and a conventional insulating organic polymer could reliably conduct electricity in up to 220 degrees Celsius (428 F). "One of the plastics transports the ch... » read more