Some of the challenges and an innovative solution that addresses them.
Development of a modern system-on-chip (SoC) device is a long and incredibly complex process. Design teams rely on a huge range of tools, technologies, and methodologies to get the job done. Given the ongoing advances in silicon technology and design architecture, the tools are in a constant state of evolution. Logic-versus-schematic (LVS) checking is one of those tools. This is one of the earliest automated steps in chip development, and some unfamiliar with its complexity might consider it “a solved problem.” However, the reality is far different. In fact, modern SoCs pose significant challenges to traditional LVS methods, and in recent years there has been considerable innovation in LVS tools. This white paper describes some of these challenges and outlines an innovative solution that addresses them.
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