Filling In The Gaps For Mixed-Signal Verification

Semiconductor Engineering sat down to discuss mixed-signal verification with Haiko Morgenstern, Mixed-Signal Verification Group Staff Engineer at Infineon; Dr. Gernot Koch, CAD Manager at Micronas; Pierluigi Daglio, AMS Design Verification Flows Manager at STMicroelectronics; and Helene Thibieroz, AMS marketing manager at Synopsys. What follows are excerpts of that discussion. For part one, click here. For part two, click here.

SE: Is analog design still lauded as being special and mysterious?

Thibieroz: Analog is really complex and getting more so. The SPICE models are getting more and more complicated, and that’s partially why now you see digitally-controlled analog architecture because the scalability fot the analog architecture is getting difficult to achieve, so you need to plug in some digital.

Daglio: In the past, in the U. S. that is driving this innovation. 10 or 15 years ago, they moved all the people to work on the digital because they were thinking that everything will be possible to do with digital. Maybe I’m wrong because I see that from Europe, but we had the perception that in the U.S. all the people who were in universities and any designer would be becoming digital and at a certain point there were no more analog designers around. Now that you have to interface all your stuff with the external world, you need the sensors and analog things to put in the phone or in the car to interface the digital, there was a lack of skill in the people. In the last 3, 4, 5 years the analog has started again and now it’s growing very much.

SE: What do you need to do mixed-signal verification better, today, from the EDA vendors?

Koch: I want to be able to mix and match abstraction levels like I can do in digital, and have different configurations, and have different implementations of the modules, the configurations I choose which implementations being elaborated and simulated. I want to do the same thing for mixed signal and the analog side because I don’t have it.. I want to decide on a block level, is this a SPICE block in my simualation now, is this an AMS block, or is this a digital real-time block that I’m modeling this — all this should more or less automatically, as much as possible, talk to each other. I want to see automation in that respect. Of course, if we allowed to dream, I would like to see the automation of the abstraction modeling — I don’t know where to get that from.

Morgenstern: Today, too much restriction from the language side. We have to think about which partitioning is allowed, which conifguration is possible in this kind of flow, then you have to choose the lanugage to the flow — this should be more flexible from the tooling side. Standardization of the testbenches and SystemVerilog 2012. When this was supported by the tools, it was a good step in the right direction to reuse the testbenches to get user defined net types.

Daglio: For sure the dream would be mix everything without thinking in the sense that now not all the configurations are supported. For example, if you have analog, digital, analog for sure the information about the current can be lost. For sure, you will also need a smart converter because there are a lot of situations in which you want to turn on and turn off part of the chip because in the new generation of the chip to save the battery, you turn off some part, and you turn on only when it’s needed but in the digital, not always you have the information about the power so digital is always working. It’s not turned off. If you want to turn it off you have to use UPF format. But if you use UPF format, mixed-signal simulation is not working well because the converter is not able to understand everything. It should be in the future. In fact, we are working with a vendor to start to support all this kind of more complex situations. Today, one big analog block, one big digital block together connected works quite well. When you have analog, digital, analog or vice versa, or analog feedback in the digital, it comes more complex. If you want to turn on and off different islands of power in the design, it becomes more difficult. In our case when we use a technology that goes up to 300 or 400 volts or a part with high power, management becomes even more difficult so step by step, we have to address all of these complexities because in reality the possibility of mixing these things are almost infinite.

Koch: [Another thing] is to speed up SPICE so we don’t need as much modeling. Modeling is only needed because SPICE is too slow.

SE: What is realistic from an EDA persective?

Thibieroz: From an EDA perspective, you mentioned performance. We offer great performance of our Fast SPICE engine but it’s never going to be enough for digital enginers — the guy in digital verification is still in 0 and 1, is used to a level of performance in terms of seconds. You’re introducing an analog engine while talking about hours, days — it’s an entirely different concept. People need to also have realistic expectations because as good as a Fast SPICE solver can be, the fact that you’re dealing with a really complex way of solving a non-linear equation is going to make it expensive — there’s no way around. We introduced multicore, we introduced a more intelligent way to basically parse the device model, and the performance you get compared to a few years ago is just phenominal. You talk to an analog engineer and they say, “This is great.” Talking to a digital engineer, “What? You want me to run in hours, not seconds? No.” In this case, there is only so much that can be done at this level. That said, you can come up with enhanced flows, you can introduce the new concept of behavioral modeling. For example, we talked about Verilog AMS — what’s very interesting is Verilog AMS is a language that is very intelligently meets analog and digital constructs, but you’ve seen moderated adoption and I think it’s because people are missing the expertise and the fact that the models have to be calibrated — they don’t have the methodology or the people. It’s an ongoing collaboration between EDA companies and customers because there’s always new needs.

Daglio: Another thing, for example is to have from the vendor application engineer that are already trained on the solution and help in the ramp up phase and use the methodology because we think it’s very important because they have direct contact with the R&D of the vendor so if you have some special need, you need the tool to ask for some improvement of some implementation, it’s very important to have this. In fact, we help our application engineer internal CAD resources and designers that are open to new things and the things that are ramping now. It’s not the fastest but you need some years to generate a flow that is working but in the end, the people are happy because a lot of people maybe were not verifying the whole system, but were verifying piece by piece and not really complete verification of the system all together, so it’s very important to set up a real mixed-signal flow that allows you to verify the whole system.

Morgenstern: It would be good if there were not only datasheets available but there needs to be verification methodologies — combinations and the languages that should be used and for the modeling guidelines.

Koch: The problem with methodologies that apply to your case but they don’t necessarily know your case. They can come up with methodologies all they want but it just doesn’t fit what I want to do.

Thibieroz: Let’s talk also about mixed-signal landscape. At the beginning of this we were thinking it’s very Customer A, B, C, D: different profile, different flow, different methodology. Ultimately, you want a flow that works for everyone but a company that is analog centric, digital centric, the way we are starting to converge more and more and find methodologies, behavioral models that are working — but it’s really going to be an ongoing effort.

Koch: We thing happening, so it’s not like it’s static. It’s just a matter of time. Little by little it will become better.