Filling In The Gaps For Mixed-Signal Verification

Experts at the table, part one: The evolving analog-digital relationship; communicating with the system; single-vendor flows; behavioral modeling; automation in the mixed-signal verification flow.


Semiconductor Engineering sat down to discuss mixed-signal Verification with Haiko Morgenstern, Mixed-Signal Verification Group Staff Engineer at Infineon; Dr. Gernot Koch, CAD Manager at Micronas; Pierluigi Daglio, AMS Design Verification Flows Manager at STMicroelectronics; and Helene Thibieroz, AMS marketing manager at Synopsys. What follows are excerpts of that discussion.

SE: What are some of the biggest challenges that engineers face today with mixed-signal verification?

Morgenstern: Design complexity. Not only the digital content is increasing but also the huge analog macros. Analog macros where we have up to 10 or 12 ADCs, which have to be verified — so those macros have a complex interface to the digital part, etc. end up in a mixed-signal verification.

Koch: The relationship between digital and analog is becoming more intricate. It’s not like you have your digital part that you can verify by itself and you have your analog part that you can verify by itself — actually analog parts are configured by digital, so you have software interacting when controlling the analog and you have analog talking to other analog parts through digital so you need to have a way of verifying all of this together.

Morgenstern: And if then the digital part is driven by a high frequency clock running at you have to simulate within a certain range — it’s nearly impossible. Such high frequencies in the digital part slows simulation down.

Thibieroz: We can see also today if you look at mixed signal verification — first it was called mixed-signal simulation, because it was a much smaller domain; typically coming from schematic, you had a digital block become mixed-signal — and then the SoC companies started driving a need for new methodologies. And especially as you see SoCs going more, because of cost, driving more and more IP, to get more complexity on the chip because you have to have more and more features, then you are in an extremely complex environment. In the case of this industry, you have a lot of different features that get added for consumers, so clearly you have a need to deal with a very complex environment, you also have a need, as Gernot just mentioned, that analog and digital used to be fairly separated; now you have digitally-controlled analog, analog-controlled digital, you have power domains: very complex environment. And the last piece — you need more and more verification. It used to be maybe you could test a few combinations — you can’t afford that today. In the automotive industry, safety requirements — same thing for cellular phone; any type of application today. Customers are faced with challenges that are more complex, so they need to do more verification, they have to adopt flows in combinations that are way more complicated than a few years ago.

Daglio: We see the lack of a profession that is a verification engineer because a normal designer, above all, people have been working for several years, they don’t have the whole picture of things. In our case, mixed-signal verification is more related to a lot of analog and a few digital blocks but digital content is growing. So you see that analog designers aren’t willing to manage digital things. They don’t like languages, they don’t want to write digital behavioral blocks but they would only like to see transistors.

SE: Why are analog designers so resistant to digital content?

Daglio: Probably because for many, many years they have done it this way. And with new hires, we try to start from the beginning to make them learn not only to design transistors but also to start at the very beginning with analog Verilog languages…and also to keep the digital concept in mind, so like with the power format UPF, that in the future will be needed. My opinion is that we need to form a new — at least in Europe — class of people, mixing the verification engineers; they have to know transistors, analog behavioral modeling, digital behavioral and power management.

Thibieroz: The behavioral modeling I’ve seen two potential challenges. One is skill and expertise – you need somebody there who is in both digital and analog. Like when you talk about Verilog AMS, it’s mixed-construct, so there’s always a potential, you create a model it is either inaccurate or it’s not efficient in terms of performance and then there’s also, later on when you any type of behavioral model … at some point you’re going to have to calibrate those. So it can become fairly expensive for a company. If you look at cycle times, if you need a few weeks to develop a model — you don’t have the expertise you need to develop the model, you need to calibrate them, well by that time you will have run everything at a transistor level if your simulator is performing well enough. Very quickly it becomes a tradeoff.

SE: Do we have an agreed upon starting point for mixed-signal verification?

Morgenstern: We have no such thing.

Koch: For one thing, it’s not really part of project planning but people start designing their things then they figure out they need to verify it.

SE: Shouldn’t verification be part of the whole project plan?

Koch: Yes, it should be.

Thibieroz: I think that’s why I find mixed-signal interesting and so challenging, it’s because you’re going to talk to Customer A, Customer B, Customer C. Customer A may just be doing functional verification. They need a high level presentation of analog, and for them it works fine…they don’t have high precision analog. If you go into European customers, they are facing the very complex analog. If you look at advanced SPICE models, for example, that you’re using, those are dealing with a lot of nonlinearity, lots of complex feedback loops, where you cannot force them to have a single flow based on functional verification real number models. And then the concept of language arises where, do you want to be more on Verilog, VHDL, Verilog AMS; it becomes also a matter of preference I think when the company has been used to special flows and special language – you come to rely on them.

Daglio: Yes, because sometimes the groups are spread all around the world. Some people prefer to use some languages in U.S., some people in Europe use other languages. Maybe you receive some netlist with a schematic coming from another site; you have to pull it all together and make everything to talk together.

Koch: In an ideal world, you don’t have to bother. In digital, this works — you can have Verilog blocks, you can have VHDL blocks, and you can have System Verilog, whatever you want, and things talk to each other and it just works. As soon as you bring in mixed signal and analog, you have Verilog AMS modeling and if you want to have System Verilog talk to Verilog AMS you have to set that up differently from if you want to have System Verilog talk to SPICE — it’s all a bit complicated.

Thibieroz: And I think it’s just going to get more complicated because you’re introducing the usage of sensors like exponentially being used and for sensors you need a high level of accuracy to be able to model them. Are you going to be doing this at a system level — it became like we are going to have to develop new flows and there is not one solution for one customer. It all depends on the amount of accuracy that they need, functionalities, performance and capacities and languages that they have.

Daglio: In the past we were also mixing tools from different vendors but now that the circuit becomes more complex, you need to have a system under one vendor because you have to keep into account too many things. In the past a converter was very easy, there was only some threshold; now they must be intelligent converters that they adopt themselves to some things. It’s better that if you have a single vendor solution, it’s better that you make all the things talk together.

SE: So, is your entire design flow from one vendor?

Daglio: The entire, no. The mixed-signal simulation, verification. For the entire, it depends in the sense that you can plug in some point tools that you need. For sure, in any case, in all the steps of the flow the relationship among the tools are becoming more tight, so it’s difficult to make a puzzle of different vendors tools and make it all work together. Also, because the vendors don’t like that their tool talks too much to the other. They like that they talk, but not too much.

Koch: I think this whole setting up the interfacing between analog and digital even within one is more than I would like. I would like to see more automation there; I’m not sure if that’s possible. I don’t really need to set up all of the voltages for high and low because it’s already in my schematic and my SPICE netlist knows it. You can find out if you look at the SPICE netlist and interpret it. Much of that can be automated, I think — or it should be.

SE: What else needs to be automated in the mixed-signal verification flow?

Daglio: We try to look around for automation of behavioral model generation for several years but we were not able to now to find an effective solution that is working well on the analog part and to try to push the designer to try these solutions. I think there is a point where it could be margin for EDA to do something in an automatic or semi-automatic generation of behavioral modeling, because as I was saying before analog designers are still very scared to learn these kinds of language.

Koch: It’s not just that. It’s also a matter of interest. the analog designer really isn’t that much interested in top level so they need an incentive if they are supposed to write models and why would they do that? Just telling them that they have to do that and it’s no benefit for themselves, doesn’t help. they need to see the benefit there.

Daglio: When we convinced an analog designer to describe their model, they made their model so precise that the simulation was slower than the transistor because they model in single spike that they will be in the circuit so in the end, it was not useful to speed up the simulation. That is another thing that we need to address.

SE: What would be a motivation for the analog designer to be willing to adopt new techniques?

Thibieroz: I’m not going to fully agree, Gernot, because that’s not what I see. We have seen the analog designers being more and more concerned because they are being asked by the digital verification team to provide models and until a few years ago, they would provide models with not necessarily calibration — because it walks, they assumed it was ok. So they are realizing the complexity of SoCs today, this approach is going to break at some point so they have a need for calibration, they have a need for stand out, they have a need of merging capability from both digital and analog verification, and it’s not only for behavioral modeling standpoint, it’s also from verification in general, to come up with a more advanced scheme. In the context of behavioral modeling, if you look at mixed signal, it started with Verilog AMS on the SPICE level. Then this was introduced to the mixed construct – analog and digital….there is clearly more and more working together to come up with new standards that could be used and that could alleviate some of those limitations because analog engineers clearly have a need for it. If they are going to have to provide behavioral models to the digital verification counterpart, making sure it is well implemented, making sure it’s calibrated , there is a lot of concern.

Koch: I don’t see the contradiction there. Sure, if you tell analog people that they have to provide the models, they need to have a way of doing that, they need to learn how to do that. Again, where is their own personal interest? How do they benefit from writing those models?

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