Fine-Pitch Copper Pillar With Bond On Lead (BOL).

Fine pitch copper (Cu) pillar bump adoption has been growing in high-performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities. Assembling such packages using a standard mass reflow (MR) process and maintaining its performance is a real and serious challenge. Typical thermal compression bonding (TCB) using non-conductive paste can be used to mitigate the assembly risk up to a certain extent of die size and package body size. On the other hand, the TCB process results in a significantly higher assembly cost due to very low throughput. The very cost-sensitive consumer market is not quite ready to adopt TCB process for this reason. To address the need for fine-pitch Cu pillar flip chip, a technology featuring copper pillar Bond-On-Lead (BOL) with enhanced processes, known as fcCuBE, delivers the cost effective, high performance packaging solution that is required by the industry.

BOL substrate technology with standard MR is becoming popular for high-performance flip chip BGA (fcBGA) assembly. fcCuBE technology provides an extended roadmap to very fine pitches (less than 100 um) for fcBGA packages, which are not available in conventional mass reflow interconnect technologies. There are some published papers that have addressed BOL or similar types of technology on small-body-size flip chip CSP type packages. However, none of the literature truly addresses the assembly challenges and risk mitigation plan for bigger-body-size fine-pitch fcBGA packages. fcCuBE provides added benefits of cost reduction through elimination of Solder on Pad (SOP) in the substrate as well as substrate layer reduction for fcBGA packages. Additionally, fcCuBE technology in a fcBGA package can drive higher I/O density, enabling advanced silicon (Si) nodes and die shrink, which can further reduce the silicon cost due to an increased number of dies per wafer. In this study a comprehensive finding on the assembly challenges, package design, and reliability, and cost data for fcBGA packages will be published.

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