The secret to nanoscale chip wiring is using capillary action to pull heat-softened copper down into tiny structures.
By Richard Lewington
If you were to slice up a microchip and take a look (you’d need a really powerful microscope, I’m afraid) you would see what looks like a nanoscale layer cake.
All the active circuit elements—transistors, memory cells, etc.—are on the bottom. The other 90% of the chip is a maze of tiny copper wires, which we call interconnects.
The history of chip development is all about shrinking circuit features. When the transistors shrink, so must the interconnects. Today, the smallest interconnects can be fewer than 200 atoms across.
Interconnects are made by filling molds of insulating material with copper. At these miniscule dimensions, completely filling these features becomes very difficult. If it’s not done just right, bubbles of vacuum, called voids, can be formed, which can create a short circuit. In the most advanced device designs, even one void can render the entire chip useless.
Applied Materials’ Endura Amber physical vapor deposition system aims to banish interconnect voids forever. The new Amber system takes advantage of capillary action to pull heat-softened copper down into even the tiniest structures.
In this video, I take a quick look at how the interconnect fabrication process is done and then demonstrate how our revolutionary copper reflow technology works.
Disaggregation and the wind-down of Moore’s Law have changed everything.
Different interconnect standards and packaging options being readied for mass chiplet adoption.
Suppliers are investing new 300mm capacity, but it’s probably not enough. And despite burgeoning 200mm demand, only Okmetic and new players in China are adding capacity.
Continued expansion in new and existing markets points to massive and sustained growth.
Aging equipment and rising demand are pushing up prices and slowing production.
Interest in this particular ISA is expanding, but the growth of other open-source hardware is less certain.
Nanosheets are likeliest option throughout this decade, with CFETs and other exotic structures possible after that.
Hybrid bonding opens up whole new level of performance in packaging, but it’s not the only improvement.
Why this is becoming a bigger issue, and what can be done to mitigate the effects.
Some 300mm tools are converted to 200mm; equipment prices and chip manufacturing costs are rising.
From low resistance vias to buried power rails, it takes multiple strategies to usher in 2nm chips.
Manufacturing 3D structures will require atomic-level control of what’s removed and what stays on a wafer.
Disaggregation and the wind-down of Moore’s Law have changed everything.
Leave a Reply