Four Steps For Static Verification Of Low Power Designs Using UPF With VC LP

Learn about four stages of IC design following the Unified Power Format (UPF), and how to use Synopsys’ VC LP static low power verification solution throughout this process.


Low power consumption has always been a key requirement for portable electrical and electronic devices. In recent years, this requirement has been extended to many more categories of end products. The electronics industry has developed a wide range of techniques for power management and has defined the Unified Power Format (UPF) to describe design intent for some of the most common methods. Successful development of low power semiconductor designs includes checking UPF descriptions as well as verifying UPF against the design at multiple stages in the project. This white paper explains how to use the Synopsys VC LP static low power verification solution throughout this process at four stages: early UPF, UPF against RTL, UPF against post-synthesis netlist, and UPF against post-place-and-route power and ground (PG) netlist.

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